Integrated circuit assemblies
Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.
1. A microelectronic assembly, comprising:
a structure including a first die, a second die, and a bonding interface between the first die and the second die; and
a third die coupled to the second die;
wherein:
the first die includes memory cells comprising backend transistors and further includes logic circuitry comprising frontend transistors,
the second die includes frontend transistors coupled to the first die, and
the microelectronic assembly further includes first vias and second vias extending through the bonding interface between the first die and the second die, wherein cross-sectional dimensions of the second vias are larger than cross-sectional dimensions of the first vias, and a pitch of the second vias is larger than a pitch of the first vias.
2. The microelectronic assembly according to claim 1 , wherein the memory cells include dynamic random-access memory cells.
3. The microelectronic assembly according to claim 2 , wherein the third die includes static random-access memory cells.
4. The microelectronic assembly according to claim 1 , wherein the memory cells include a non-hierarchical memory.
5. The microelectronic assembly according to claim 1 , wherein the third die includes a hierarchical memory.
6. The microelectronic assembly according to claim 1 , wherein the backend transistors of the memory cells of the first die are coupled in pairs of backend transistors, and wherein, for an individual pair of the pairs:
the individual pair includes a first backend transistor and a second backend transistor,
the first and second backend transistors share a continuous layer of a semiconductor material,
a gate contact and a first contact for an individual one of the first and second backend transistors are over a first surface of the semiconductor material, and
a second contact for each of the first and second backend transistors is a shared contact over a second surface of the semiconductor material, the second surface being opposite the first surface, wherein one of the first contact and the second contact is a source contact and another one of the first contact and the second contact is a drain contact.
7. The microelectronic assembly according to claim 6 , wherein the gate contact for the first backend transistor and the gate contact for the second backend transistor are over a portion of the semiconductor material that is between a portion of the semiconductor material in conductive contact with the first contact of the first backend transistor and a portion of the semiconductor material in conductive contact with the first contact of the second backend transistor.
8. The microelectronic assembly according to claim 1 , wherein the bonding interface between the first die and the second die is a hybrid bonding interface.
9. The microelectronic assembly according to claim 1 , wherein the pitch of the second vias is between about 10 and 25 micrometers.
10. The microelectronic assembly according to claim 1 , wherein the cross-sectional dimensions of the second vias are between about 7 and 11 micrometers, and the cross-sectional dimensions of the first vias are between about 2 and 4 micrometers.
11. The microelectronic assembly according to claim 1 , further comprising a glass structure and a bonding material, wherein the bonding material is between a surface of the first die and a surface of the glass structure.
12. The microelectronic assembly according to claim 11 , wherein the glass structure includes quartz.
13. The microelectronic assembly according to claim 11 , wherein a thickness of the first die is smaller than a thickness of the glass structure.
14. The microelectronic assembly according to claim 11 , wherein the bonding material includes silicon, nitrogen, and carbon.
15. The microelectronic assembly according to claim 1 , wherein the first vias are signal vias and the second vias are power vias.
16. The microelectronic assembly according to claim 1 , wherein the frontend transistors of the second die are to at least partially control operation of the first die.
17. The microelectronic assembly according to claim 1 , wherein the pitch of the first vias is between about 2 and 12 micrometers.
18. A microelectronic assembly, comprising:
a compute die; and
a memory die, coupled to the compute die, the memory die comprising:
a data block that includes a memory array circuit, where the memory array circuit includes a memory array and a plurality of first vias to communicate signals with the memory array, and
a plurality of second vias to provide power to components of the data block, wherein:
the plurality of second vias and the plurality of first vias extend between opposing faces of the memory die,
the plurality of first vias are arranged along a first line,
the plurality of second vias are arranged along a second line, and
the second line is substantially perpendicular to the first line.
19. The microelectronic assembly according to claim 18 , wherein the first line is substantially parallel to an edge of the memory array.
20. The microelectronic assembly according to claim 19 , wherein the second line is substantially parallel to an edge of the data block.
21. The microelectronic assembly according to claim 18 , wherein:
the memory array is one of a plurality of memory arrays included in the memory array circuit, and each of the plurality of memory arrays is associated with a respective plurality of first vias, and
the memory array circuit is one of a plurality of memory array circuits included in the data block, and each of the plurality of memory array circuits is associated with a respective plurality of second vias.
22. An integrated circuit (IC) package, comprising:
a microelectronic assembly; and
a further IC component, the further IC component coupled to the microelectronic assembly,
wherein the microelectronic assembly includes:
a structure including a first die, a second die, and a bonding interface between the first die and the second die, and
a third die coupled to the second die;
wherein:
the first die includes memory cells comprising backend transistors and further includes logic circuitry comprising frontend transistors,
the second die includes frontend transistors coupled to the first die, and
the microelectronic assembly further includes first vias and second vias extending through the bonding interface between the first die and the second die, wherein cross-sectional dimensions of the second vias are larger than cross-sectional dimensions of the first vias, and a pitch of the second vias is larger than a pitch of the first vias.
23. The IC package according to claim 22 , wherein the further component is a package substrate and where the package substrate includes one or more of a ceramic material and an organic material.
24. The IC package according to claim 22 , wherein the further component is a printed circuit board, a flexible substrate, or an interposer.
25. The IC package according to claim 22 , further comprising interconnects between the further component and the microelectronic assembly, wherein the interconnects include one or more solder bumps, solder posts, or bond wires.
26. The IC package according to claim 22 , further comprising a heat spreader.