Granted Patent B2

US 12,615,087 · App. 17/395,903 · Granted Apr 28, 2026

Inventors: Nikolaos Pleros (Salonika, GR); David Lazovsky (Los Gatos, CA); George Giamougiannis (Salonika, GR); Apostolos Tsakyridis (Salonika, GR); Angelina Totovic (Central Macedonia, GR)

Assignee: Celestial AI Inc.

H04B10/27G02F1/225G06N3/04H04B10/07H04Q11/0005

Abstract

Claims (33)

1 . A computing system comprising:

a photonic integrated circuit (PIC) implementing one or more computational layers, the PIC comprising:

one or more coherent photonic crossbars each configured to modulate a plurality of optical input signals to impart computational weights associated with a plurality of sets of weights onto the optical input signals to create weighted optical input signals, and to coherently combine the weighted optical input signals to generate optical output signals encoding computational outputs associated with the plurality of sets of weights,

at least one of the one or more coherent photonic crossbars comprising a plurality of electronically controlled modulators to impart computational inputs onto coherent optical carrier signals to generate the plurality of optical input signals, and

at least one of the one or more coherent photonic crossbars comprising a plurality of photodetectors to generate analog electronic output signals based on the optical output signals; and

a mixed-signal electronic integrated circuit (EIC) comprising:

driver circuitry to control the modulators in the PIC in accordance with the computational inputs, and

processing circuitry to process the analog electronic output signals, the processing being performed at least partially digitally.

2 . The computing system of claim 1 , wherein the one or more coherent photonic crossbars implement multiple computational layers.

3 . The computing system of claim 2 , wherein the analog electronic output signals associated with one of the multiple computational layers are processed to generate control signals for the driver circuitry associated with the computational inputs of another one of the computational layers.

4 . The computing system of claim 3 , wherein at least one of the one or more coherent photonic crossbars comprises a plurality of additional electronically controlled modulators to impart the computational weights onto the optical input signals, and wherein the EIC further comprises additional driver circuitry to control the additional modulators.

5 . The computing system of claim 4 , wherein the one of the computational layers and the other one of the computational layers are implemented by a single one of the one or more coherent photonic crossbars, and wherein the additional driver circuitry controls the additional modulators in accordance with one set of computational weights to implement the one of the computational layers and in accordance with another set of computational weights to implement the other one of the computational layers.

6 . The computing system of claim 4 , wherein the EIC further comprises memory storing the computational weights and digital-to-analog converters to generate, from the computational weights, control signals for the additional driver circuitry.

7 . The computing system of claim 4 , wherein the additional electronically controlled modulators comprise pairs of an amplitude modulator and a phase shifter to impart signed computational weights onto electric fields of the optical input signals.

8 . The computing system of claim 3 , wherein the one of the computational layers and the other one of the computational layers are implemented by two coherent photonic crossbars.

9 . The computing system of claim 2 , wherein the multiple computational layers are implemented by multiple coherent photonic crossbars, and wherein the optical output signals of at least one of the coherent photonic crossbars are provided to another one of the coherent photonic crossbars as the optical input signals.

10 . The computing system of claim 1 , further comprising at least one of optical amplifiers in the PIC to amplify the optical output signals or electronic amplifiers in the processing circuitry to amplify the analog electronic output signal.

11 . The computing system of claim 1 , wherein the one or more computational layers represent one or more neural network layers, the plurality of sets of weights represent a plurality of neurons, and the computational outputs are linear neuron outputs.

12 . The computing system of claim 11 , wherein the processing circuitry applies a non-linear electronic activation function to the analog electronic signals either in an analog domain or in a digital domain following analog-to-digital conversion.

13 . The computing system of claim 11 , wherein the PIC further comprises non-linear activation units associated with the neurons of at least one of the one or more coherent photonic crossbars, the non-linear optical activation units configured to apply an optical non-linearity to the optical output signals encoding the linear neurons outputs to thereby generate optical output signals encoding non-linear neuron outputs.

14 . The computing system of claim 11 , wherein the digital processing comprises a neural-network-layer operation.

15 . The computing system of claim 14 , wherein the neural-network-layer operation implements one of a pooling layer or a fully connected layer.

16 . The computing system of claim 11 , wherein the digital processing comprises an image pre-processing operation for image input to the one or more neural network layers or a post-processing operation of output generated by the one or more neural network layers.

17 . The computing system of claim 16 , wherein the digital processing comprises adjusting stored neural network weights to enable structural sparsity.

18 . The computing system of claim 11 , wherein at least one of the PIC or the EIC is configured to perform mixed-precision operations.

19 . The computing system of claim 11 , wherein the EIC further comprises a graphic processing unit (GPU) core to perform at least part of the digital processing.

20 . The computing system of claim 1 , wherein the EIC further comprises on-chip memory.

21 . The computing system of claim 1 , further comprising an electronic interface between the PIC and the EIC, the electronic interface having a power consumption of less than 3 pJ per bit of data converted from an optical domain to a digital electronic domain or from a digital electronic domain to an optical domain.

22 . The computing system of claim 1 , the PIC further comprising an optical splitter that receives carrier light from a light engine and splits it into the coherent optical carrier signals.

23 . The computing system of claim 22 , wherein the light engine comprises a plurality of lasers generating light at multiple wavelengths and a multiplexer to combine the light at the multiple wavelengths into multiplexed carrier light.

24 . The computing system of claim 1 , the PIC further comprising an optical interface that receives carrier light from a source external to the PIC, the optical interface comprising at least one of an edge coupler, inverted taper coupler, or grating coupler.

25 . The computing system of claim 24 , wherein the optical interface comprises at least one of an edge coupler, an inverted taper coupler, or a grating coupler.

26 . The computing system of claim 1 , wherein the digital processing comprises operations performed at higher bit precision than operations performed in the PIC.

Assignments (2)

Continuity (2)

References Cited (374)