IP Library › Granted Patent US 12,733,214
Granted Patent B2
US 12,733,214 · App. 17/527,975 · Granted Sep 8, 2026

Surface-doped channels for threshold voltage modulation

Inventors: Hsiao-Chun Chang (Hsinchu, TW); Guan-Jie Shen (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10D30/6757H10D30/031H10D30/6735H10D62/121H10D62/292H10D62/307H10D62/8171H10D30/014H10D30/024H10D30/6211
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Quick Facts
Patent No.
US 12,733,214
App. No.
17/527,975
Granted
Sep 8, 2026
Kind
B2
Abstract

GAAFET threshold voltages are tuned by introducing dopants into a channel region. In a GAAFET that has a stacked channel structure, dopants can be introduced into multiple channels by first doping nano-structured layers adjacent to the channels. Then, by an anneal operation, dopants can be driven, from surfaces of the doped layers into the channels, to achieve a graduated dopant concentration profile. Following the anneal operation and after the dopants are diffused into the channels, depleted doped layers can be replaced with a gate structure to provide radial control of current in the surface-doped channels.

Claims (43)

1 . A method, comprising:

forming a superlattice on fins on a substrate, the superlattice comprising doped nanostructured layers and channel layers, wherein the doped nanostructure layers comprise p-type or n-type dopants;

forming isolation regions on the substrate;

forming a sacrificial structure on the superlattice;

etching back the superlattice in source/drain regions, while maintaining the superlattice in a gate region;

forming inner spacers and epitaxial source/drain regions;

annealing, the doped nanostructured layers with the inner spacers separating the epitaxial source/drain regions from the doped nanostructured layers to drive in the p-type or n-type dopants from the doped nano-structured layers into the channel layers and form a dopant concentration gradient in each of the channel layers;

removing the doped nanostructured layers from an annealed channel region;

forming an inter-layer dielectric over the epitaxial source/drain regions; and

replacing the sacrificial structure with a gate structure.

2 . The method of claim 1 , wherein forming the epitaxial source/drain regions comprises growing source/drain regions from channel layers of the superlattice, wherein the source/drain regions and the channel layers are made of a same material.

3 . The method of claim 1 , wherein forming the epitaxial source/drain regions comprises incorporating dopants in-situ during an epitaxial growth process.

4 . The method of claim 1 , wherein forming the epitaxial source/drain regions comprises doping the epitaxial source/drain regions with impurities of opposite polarity with respect to the p-type or n-type dopants in the doped nano-structured layers.

5 . The method of claim 1 , wherein annealing the superlattice comprises forming a graduated dopant profile in the channel layers with a dopant concentration range from about 1×10 12 cm −3 to about 1×10 15 cm −3 .

6 . The method of claim 1 , wherein forming the superlattice comprises using one or more masks to select materials and dopant types for the channel layers.

7 . The method of claim 6 , wherein using the one or more masks comprises selecting materials and dopant types for the channel layers to form different compositions and doping profiles on the substrate.

8 . The method of claim 6 , wherein using the one or more masks comprises blocking a first area of the substrate to deposit a superlattice on a second area of the substrate.

9 . A method, comprising:

forming a fin structure on a substrate;

growing a superlattice on the fin structure, wherein the superlattice comprises first nanostructure layers and second nanostructure layers stacked alternatingly, and wherein the first nanostructure layers comprise first type dopants, wherein the first type dopants comprise p-type or n-type dopants;

depositing inner spacers on side surfaces of the first nanostructure layers;

growing epitaxial source/drain regions on side surfaces of the second nanostructure layers;

forming, by annealing the first and second nanostructure layers with the inner spacers separating the first nanostructure layers and the epitaxial source/drain regions, a dopant concentration gradient in each of the second nanostructure layers;

removing the first nanostructured layers; and

forming a gate structure around each of the second nanostructure layers.

10 . The method of claim 9 , wherein forming the dopant concentration gradient comprises forming the dopant concentration gradient extending radially inward in each of the second nanostructure layers, and wherein the doping concentration decreases from surfaces of each of the second nanostructure layers to central regions of each of the second nanostructure layers.

11 . The method of claim 10 , wherein forming the dopant concentration gradient comprises:

controlling the doping concentration at the surfaces of each of the second nanostructure layers to be about 1×10 15 cm −3 ; and

controlling the doping concentration at the central regions of each of the second nanostructure layers to be about 1×10 12 cm −3 .

12 . The method of claim 9 , wherein growing the epitaxial source/drain regions comprises doping the epitaxial source/drain regions with second type dopants opposite to the first type dopants.

13 . The method of claim 9 , wherein forming the dopant concentration gradient comprises annealing the superlattice at a temperature between about 600° C. and about 1300° C.

14 . A method, comprising:

forming a multi-layer stack that comprises a first nanostructure layer and a second nanostructure layer in contact with the first nanostructure layer, wherein the first nanostructure layer comprises epitaxial silicon germanium (SiGe) doped with first type dopants;

etching the multi-layer stack to form a fin structure;

forming an epitaxial source/drain region adjacent to the fin structure, wherein forming the epitaxial source/drain region comprises introducing second type dopants in the epitaxial source/drain region;

performing, after introducing the second type dopants in the epitaxial source/drain region, an annealing process to concurrently activate the second type dopants in the epitaxial source/drain region and diffuse the first type dopants from the first nanostructure layer to the second nanostructure layer; and

replacing the first nanostructure layer by a gate structure surrounding the second nanostructure layer.

15 . The method of claim 14 , wherein a concentration gradient of the first type dopants is along a direction perpendicular to a top surface of the multi-layer stack.

16 . The method of claim 14 , wherein etching the multi-layer stack comprises forming coplanar side surfaces of the first and second nanostructure layers.

17 . The method of claim 14 , wherein the first type dopants comprise boron, and wherein the second type dopants comprise phosphorous.

18 . The method of claim 1 , wherein annealing the superlattice comprises doping first and second portions of each of the channel layers, wherein the first and second portions are adjacent to the inner spacers and the doped nanostructure layers, respectively, and wherein a first dopant concentration of the first portion is greater than a second dopant concentration of the second portion.

19 . The method of claim 9 , further comprising forming a doping profile in each of the second nanostructure layers, wherein the doping profile comprises a first dopant concentration of a first region adjacent to the gate structure less than a second dopant concentration of a second region adjacent to the inner spacers.

20 . The method of claim 14 , wherein performing the annealing process comprises forming a surface-doped channels in the second nanostructure layer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 58388 FRAME 899. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNEE. Recorded Jul 15, 2026
From: CHANG, HSIAO-CHUN; SHEN, GUAN-JIE
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 075983/0542 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2021
From: CHANG, HSIAO-CHUN; SHEN, GUAN-JIE
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 058388/0899 →
Continuity (2)
Provisional Application 63185741 · May 7, 2021
Related Publication 20220359768A1 · Nov 10, 2022
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