Advanced copper interconnects with hybrid microstructure
A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.
1. A method of forming an integrated circuit, comprising:
providing, in a dielectric layer on a wafer, (i) a first narrow-line trench and (ii) a second narrow-line trench, wherein the first narrow-line trench has a depth d 1 , wherein the second narrow-line trench has a depth d 2 , and wherein d 1 is less than d 2 ;
depositing a liner material on
a bottom and sidewalls of the first narrow-line trench,
a bottom and sidewalls of the second narrow-line trench, and
the dielectric layer;
depositing copper on the liner material; and
annealing the deposited copper such that (i) the copper in the first narrow-line trench comprises bamboo microstructure and (ii) the copper in the second narrow-line trench comprises polycrystalline microstructure.
2. The method of claim 1 , wherein a cross-section of the copper in the first narrow-line trench consists of bamboo microstructure.
3. The method of claim 1 , wherein a cross-section of the copper in the second narrow-line trench consists of polycrystalline microstructure.
4. The method of claim 1 , wherein a cross-section of the copper in the second narrow-line trench comprises a top portion comprising bamboo microstructure and a bottom portion comprising polycrystalline microstructure.
5. The method of claim 1 , wherein the liner material comprises tantalum.
6. The method of claim 1 , wherein the liner material comprises cobalt.
7. The method of claim 1 , wherein the liner material comprises ruthenium.
8. The method of claim 1 , wherein the dielectric layer comprises silicon, carbon, and oxygen.
9. The method of claim 1 , wherein the dielectric layer comprises silicon, carbon, oxygen, and hydrogen.
10. The method of claim 1 , wherein (i) a width of the first narrow-line trench and (ii) a width of the second narrow-line trench are each less than 75 nm.
11. A method of forming an integrated circuit, comprising:
providing, in a dielectric layer on a wafer, (i) a first narrow-line trench and (ii) a second narrow-line trench, wherein the first narrow-line trench has a depth d 1 , wherein the second narrow-line trench has a depth d 2 , and wherein d 1 is less than d 2 ;
depositing a liner material on
a bottom and sidewalls of the first narrow-line trench,
a bottom and sidewalls of the second narrow-line trench, and
the dielectric layer;
depositing copper on the liner material to fill the first and second narrow-line trenches; and
annealing the deposited copper such that (i) copper comprising bamboo microstructure extends to the liner material at the bottom of the first narrow-line trench and (ii) copper comprising bamboo microstructure extends towards the liner material at the bottom of the second narrow-line trench and ends at a depth above d 2 .
12. The method of claim 11 , wherein a cross-section of the copper in the second narrow-line trench comprises polycrystalline microstructure.
13. The method of claim 11 , wherein a cross-section of the copper in the second narrow-line trench comprises a top portion comprising bamboo microstructure and a bottom portion comprising polycrystalline microstructure.
14. The method of claim 11 , wherein the liner material comprises tantalum.
15. The method of claim 11 , wherein the liner material comprises cobalt.
16. The method of claim 11 , wherein the liner material comprises ruthenium.
17. The method of claim 11 , wherein the dielectric layer comprises silicon, carbon, and oxygen.
18. The method of claim 11 , wherein the dielectric layer comprises silicon, carbon, oxygen, and hydrogen.
19. The method of claim 11 , wherein (i) a width of the first narrow-line trench and (ii) a width of the second narrow-line trench are each less than 75 nm.