Display device
To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.
1. A display device comprising:
a pixel portion; and
a driver circuit electrically connected to the pixel portion, the driver circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor; and
a fifth transistor,
wherein one of a source and a drain of the first transistor is directly connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the third wiring,
wherein a gate of the third transistor is directly connected to a gate of the second transistor,
wherein the gate of the third transistor is electrically connected to a fourth wiring,
wherein a gate of the fourth transistor is directly connected to the first wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring,
wherein a gate of the fifth transistor is electrically connected to a sixth wiring, and
wherein a clock signal is input to the first wiring.
2. A display device comprising:
a pixel portion; and
a driver circuit electrically connected to the pixel portion, the driver circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor; and
a fifth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the third wiring,
wherein a gate of the third transistor is directly connected to a gate of the second transistor,
wherein the gate of the third transistor is electrically connected to a fourth wiring,
wherein a gate of the fourth transistor is directly connected to the first wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring,
wherein a gate of the fifth transistor is electrically connected to a sixth wiring,
wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the second transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the third transistor,
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor, and
wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fifth transistor.
3. The display device according to claim 2 ,
wherein the one of the source and the drain of the first transistor is directly connected to the first wiring.
4. The display device according to claim 2 ,
wherein a clock signal is input to the first wiring.