Contact resistance reduction employing germanium overlayer pre-contact metalization
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
1. A method for fabricating a low-contact resistance FET, the method comprising:
forming a gate-stack on a substrate, the gate-stack comprising a gate electrode, dielectric sidewall spacers on opposite lateral sides of the gate electrode and a gate dielectric configured to provide isolation between the substrate and the gate electrode;
etching a source cavity and a drain cavity in the substrate on opposite sides of the gate-stack;
depositing a boron-doped buffer into each of the source and drain cavities, the boron-doped buffer comprising at least 50% germanium with a doping concentration in excess of 1e20 cm −3 ;
depositing germanium-silicon onto the boron-doped buffers into the source and drain cavities so as to substantially fill the source and drain cavities; and
depositing a boron-doped cap onto the germanium-silicon deposited onto the boron-doped buffers.
2. The method of claim 1 , wherein depositing the boron-doped buffer into each of the source and drain cavities comprises:
epitaxially growing germanium-silicon on exposed surfaces of the source and drain cavities.
3. The method of claim 2 , wherein germanium concentration of the germanium-silicon is graded from a first concentration of germanium at a cavity/buffer interface to a second concentration of germanium at a top surface.
4. The method of claim 3 , wherein the first concentration of germanium is less than the second concentration of germanium.
5. The method of claim 4 , wherein the second concentration of germanium is greater than 50%.
6. The method of claim 1 , wherein depositing germanium-silicon onto the boron-doped buffers into the source and drain cavities comprises:
epitaxially growing germanium-silicon on the boron-doped buffers.
7. The method of claim 1 , further comprising:
forming a germanide on the boron-doped cap.
8. The method of claim 7 , wherein forming the germanide on the boron-doped cap comprises:
depositing a metal onto the boron-doped cap; and
forming the germanide via a heat treatment.
9. The method of claim 7 , further comprising:
depositing a contact adhesion layer onto the germanide.
10. The method of claim 9 , wherein the contact adhesion layer is titanium nitride.
11. The method of claim 1 , wherein the boron-doped cap has a boron concentration in excess of 1e20 cm −3 .
12. The method of claim 1 , wherein the boron-doped cap has a boron concentration in excess of 1e21 cm −3 .
13. The method of claim 1 , wherein a germanium concentration of the boron-doped cap is greater than 90%.
14. The method of claim 1 , wherein the boron-doped cap has a thickness between 50 and 250 angstroms.
15. A low-contact resistance FET comprising:
a substrate;
a gate-stack on the substrate, the gate-stack included a gate electrode, dielectric sidewall spacers on opposite lateral sides of the gate electrode and a gate dielectric configured to provide isolation between the substrate and the gate electrode;
a source cavity and a drain cavity etched in the substrate on opposite sides of the gate-stack;
a boron-doped buffer deposited into each of the source and drain cavities, the boron-doped buffer comprising at least 50% germanium with a doping concentration in excess of 1e20 cm −3 ;
germanium-silicon deposited onto the boron-doped buffers into the source and drain cavities so as to substantially fill the source and drain cavities; and
a boron-doped cap deposited onto the germanium-silicon deposited onto the boron-doped buffers.
16. The low-contact resistance FET of claim 15 , wherein the boron-doped cap has a boron concentration in excess of 1e20 cm −3 .
17. The low-contact resistance FET of claim 15 , wherein the boron-doped cap has a boron concentration in excess of 1e21 cm −3 .
18. The low-contact resistance FET of claim 15 , wherein a germanium concentration of the boron-doped cap is greater than 90%.
19. The low-contact resistance FET of claim 15 , wherein the boron-doped cap has a thickness between 50 and 250 angstroms.