Three-dimensional memory device containing epitaxial pedestals and top source contact
A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel.
1. A semiconductor structure, comprising:
a doped single crystalline semiconductor material layer;
a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer;
a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer;
an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer;
a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer;
a memory film and a vertical semiconductor channel located within the memory opening, wherein the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer; and
a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel;
wherein the single crystalline semiconductor pedestal comprises a coreless epitaxial semiconductor pedestal comprising a cylindrical epitaxial semiconductor portion and an annular laterally-protruding portion having a greater lateral extent than the cylindrical epitaxial semiconductor portion, wherein the coreless epitaxial semiconductor pedestal comprises a cylindrical inner sidewall that extends through the cylindrical epitaxial semiconductor portion and through the annular laterally-protruding portion and contacts the vertical semiconductor channel, and wherein the cylindrical epitaxial semiconductor portion comprises a cylindrical outer sidewall that contacts the doped single crystalline semiconductor material layer.
2. The semiconductor structure of claim 1 , wherein the annular laterally-protruding portion comprises an annular horizontal surface having an inner periphery that is adjoined to a closed edge of the cylindrical outer sidewall.
3. The semiconductor structure of claim 2 , wherein the annular laterally-protruding portion comprises a convex or faceted surface that is adjoined to an outer periphery of the annular horizontal surface of the annular laterally-protruding portion.
4. The semiconductor structure of claim 3 , wherein the convex or faceted surface of the annular laterally-protruding portion contacts the dielectric isolation layer.
5. The semiconductor structure of claim 1 , wherein a periphery of an interface between the annular laterally-protruding portion and the dielectric isolation layer is in contact with an insulating layer within the alternating stack.
6. The semiconductor structure of claim 1 , wherein the memory film is vertically spaced from the coreless epitaxial semiconductor pedestal by a portion of the vertical semiconductor channel that directly contacts a sidewall surface of one of the insulating layers within the alternating stack.
7. The semiconductor structure of claim 6 , wherein an interface between the vertical semiconductor channel and the one of the insulating layers within the alternating stack is vertically coincident with an interface between the memory film and the alternating stack.
8. The semiconductor structure of claim 1 , wherein the vertical semiconductor channel comprises a single crystalline semiconductor material that continuously extends through each electrically conductive layer within the alternating stack.
9. The semiconductor structure of claim 8 , wherein the single crystalline semiconductor material of the vertical semiconductor channel is in epitaxial alignment with a single crystalline semiconductor material of the coreless epitaxial semiconductor pedestal.
10. The semiconductor structure of claim 8 , wherein:
the vertical semiconductor channel comprises a single crystalline silicon channel;
the doped single crystalline semiconductor material layer comprises a doped single crystalline silicon layer;
the metal or metal alloy source contact layer comprises an aluminum layer which contacts the back side of the doped single crystalline silicon layer; and
the coreless epitaxial semiconductor pedestal comprises a single crystalline silicon pedestal.
11. The semiconductor structure of claim 8 , further comprising a drain region located at an end of the vertical semiconductor channel that is distal from the doped single crystalline semiconductor material layer.
12. The semiconductor structure of claim 1 , wherein:
the vertical semiconductor channel comprises a polysilicon channel;
the doped single crystalline semiconductor material layer comprises a doped single crystalline silicon layer;
the metal or metal alloy source contact layer comprises an aluminum layer which contacts the back side of the doped single crystalline silicon layer; and
the coreless epitaxial semiconductor pedestal comprises a single crystalline silicon pedestal.
13. The semiconductor structure of claim 12 , further comprising a dielectric core vertically extending through the alternating stack, the dielectric isolation layer, and a portion of the doped single crystalline semiconductor material layer that is proximal to the dielectric isolation layer, and laterally surrounded by the vertical semiconductor channel.
14. The semiconductor structure of claim 1 , further comprising a logic die comprising a peripheral circuitry bonded to the alternating stack.