Poly-silicon based word line for 3D memory
Memory devices and methods of manufacturing memory devices are provided. The device and methods described decrease the resistivity of word lines by forming word lines comprising low resistivity materials. The low resistivity material has a resistivity in a range of from 5 μΩcm to 100 μΩcm. Low resistivity materials may be formed by recessing the word line and selectively growing the low resistivity materials in the recessed portion of the word line. Alternatively, low resistivity materials may be formed by depositing a metal layer and silicidating the metal in the word line region and in the common source line region.
1 . A semiconductor device comprising:
a memory stack on a common source line, the memory stack comprising alternating silicon oxide layers and word lines, the word lines comprising silicon and a low resistivity material, the low resistivity material selected from the group consisting of tungsten (W), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), nickel (Ni), molybdenum silicide (MoSi), titanium silicide (TiSi), platinum silicide (PtSi), tantalum silicide (TaSi), ruthenium silicide (RuSi);
a filled slit completely filled with an insulator material and extending through the memory stack into the common source line and having a slit region comprising the low resistivity material, the low resistivity material formed at least on an end of the word line facing the slit region and on an end of the common source line facing the slit region; and
a plurality of memory strings extending through the memory stack adjacent to the filled slit, wherein each of the plurality of memory strings comprises a plurality of transistor layers.
2 . The semiconductor device of claim 1 , wherein the low resistivity material has a thickness in a range of from 5 nm to 150 nm.
3 . The semiconductor device of claim 1 , wherein each of the plurality of transistor layers comprises one or more of a blocking oxide layer, a nitride layer, a tunnel oxide layer, a poly-silicon channel layer, and a core oxide layer.
4 . The semiconductor device of claim 3 , further comprising a bitline pad on a top surface of the plurality of transistor layers.
5 . The semiconductor device of claim 4 , further comprising a bitline stud extending from a top surface of the bitline pad.
6 . The semiconductor device of claim 1 , wherein the low resistivity material has a resistivity in a range of from 5 μΩcm to 100 μΩcm.
7 . The semiconductor device of claim 1 , where the insulator material is selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride.
8 . The semiconductor device of claim 7 , wherein the insulator material consists essentially of silicon oxide.