RRAM process integration scheme and cell structure with reduced masking operations
Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.
1. A resistive random access memory (RRAM) comprising:
one or more bottom electrodes comprised of tungsten;
one or more switching layers comprised of hafnium oxide disposed above the one or more bottom electrodes, the one or more switching layers comprising a switchable filament;
one or more resistive layers disposed above the one or more switching layers, wherein the one or more resistive layers are comprised of a conductive metal oxide; and
wherein each bottom electrode comprises a via disposed below the one or more switching layers, wherein the via is directly in contact with the switching layer and the via is comprised of tungsten.
2. The RRAM of claim 1 , further comprising:
one or more bit lines disposed above the one or more resistive layers.
3. The RRAM of claim 2 , wherein the one or more resistive layers extend laterally to connect two or more RRAM cells along the one or more bit lines.
4. The RRAM of claim 2 , further comprising:
one or more non-linear device layers disposed below the one or more bit lines and above the one or more resistive layers.
5. The RRAM of claim 4 , wherein the one or more non-linear device layers comprise a metal-insulator-metal structure.
6. The RRAM of claim 2 , wherein the one or more bottom electrodes comprise one or more word lines that are orthogonal to the one or more bit lines.
7. The RRAM of claim 6 , further comprising:
one or more non-linear device layers disposed above the one or more word lines and below the one or more switching layers.
8. The RRAM of claim 7 , wherein the one or more non-linear device layers comprise a metal-insulator-metal structure.
9. A resistive random access memory (RRAM) comprising:
one or more switching layers;
one or more resistive layers disposed above the one or more switching layers, wherein the one or more resistive layers extend laterally to connect two or more memory cells, and the one or more resistive layers are comprised of a conductive metal oxide;
one or more top electrodes disposed above the one or more resistive layers; and
a via disposed below the one or more switching layers, wherein the via is directly in contact with the one or more switching layers, and wherein the via is comprised of tungsten.
10. The RRAM of claim 9 , wherein the one or more switching layers comprise a switchable filament.
11. The RRAM of claim 9 , further comprising one or more bottom electrodes disposed below the one or more switching layers, wherein the one or more bottom electrodes comprise the via.
12. The RRAM of claim 11 , wherein the one or more bottom electrodes are comprised of tungsten.
13. The RRAM of claim 9 , wherein a material of the one or more switching layers comprises a transition metal oxide.
14. The RRAM of claim 9 , wherein a material of the one or more switching layers comprises tantalum oxide.
15. The RRAM of claim 9 , wherein a material of the one or more switching layers comprises titanium oxide or hafnium oxide.
16. The RRAM of claim 9 , wherein the one or more top electrodes correspond to a metallization layer used for connections on a semiconductor device.
17. The RRAM of claim 9 , wherein the one or more switching layers have a resistance that changes upon application of a voltage.
18. The RRAM of claim 9 , further comprising:
one or more bit lines disposed above the one or more resistive layers, wherein the one or more resistive layers extend laterally to connect the two or more RRAM cells along the one or more bit lines.
19. The RRAM of claim 1 , wherein the via serves as a conductive path between the one or more switching layers and a semiconductor component underlying the switching layer.