3D-stacked semiconductor device including gate structure with RMG inner spacer protecting lower work-function metal layer
Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.
1 . A multi-stack semiconductor device comprising:
a substrate;
a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure comprising a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and
an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure comprising an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern,
wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and
wherein a replacement metal gate (RMG) inner spacer is formed between and contact a top surface of the lower work-function metal layer and a bottom surface of the upper work-function metal layer at selected regions where the lower channel structure is not vertically overlapped by the upper channel structure.
2 . The multi-stack semiconductor device of claim 1 , wherein the top surface of the lower work-function metal layer on which the RMG inner spacer is formed is lower than a level of a top surface of the lower gate metal pattern.
3 . The multi-stack semiconductor device of claim 2 , wherein a top surface of the RMG inner spacer is coplanar with the top surface of the lower gate metal pattern.
4 . The multi-stack semiconductor device of claim 1 , wherein the RMG inner spacer is formed in a plurality of grooves, and
wherein a portion of the lower gate metal pattern is formed between two adjacent grooves among the plurality of grooves.
5 . The multi-stack semiconductor device of claim 4 , wherein the two adjacent grooves are extended in a channel-width direction.
6 . The multi-stack semiconductor device of claim 4 , wherein two grooves among the plurality of grooves are respectively formed at both sides of the lower gate metal pattern.
7 . The multi-stack semiconductor device of claim 1 , wherein a portion of the upper work-function metal layer is laterally extended above the lower channel structure where the lower channel structure is not overlapped by the upper channel structure.
8 . The multi-stack semiconductor device of claim 7 , wherein the RMG inner spacer is formed below a level of the laterally extended portion of the upper work-function metal layer.
9 . The multi-stack semiconductor device of claim 8 , wherein the laterally extended portion of the upper work-function metal layer is interposed between the lower gate metal pattern and the upper gate metal pattern.
10 . The multi-stack semiconductor device of claim 1 , wherein a diffusion break structure or a gate-cut isolation structure is formed at a side of the multi-stack semiconductor device, and a portion of the lower work-function metal layer and a portion of the upper work-function metal layer are formed along a sidewall of the diffusion break structure or the gate-cut isolation structure, and
wherein the RMG inner spacer is formed between the portion of the lower work-function metal layer and the portion of the upper work-function metal layer along the sidewall.
11 . The multi-stack semiconductor device of claim 1 , wherein at least the lower field-effect transistor is a nanosheet transistor, and the lower channel structure comprises a plurality of nanosheet layers vertically stacked on the substrate.
12 . The multi-stack semiconductor device of claim 11 , wherein the RMG inner spacer contacts at least one of the lower gate dielectric layer and the upper gate dielectric layer along a channel-length direction.
13 . The multi-stack semiconductor device of claim 1 , wherein the RMG inner spacer contacts a side surface of a portion of the lower gate metal pattern along a channel-length direction.
14 . The multi-stack semiconductor device of claim 13 , wherein the RMG inner spacer is between a portion of the lower gate metal pattern and at least one of the lower gate dielectric layer and the upper gate dielectric layer along the channel-length direction.
15 . A multi-stack semiconductor device comprising:
a substrate;
a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure comprising a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and
an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure comprising an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern,
wherein a replacement metal gate (RMG) inner spacer is formed between and contacts a top surface of the lower work-function metal layer and a bottom surface of the upper work-function metal layer at a side of the lower gate metal pattern in a channel-width direction.
16 . The multi-stack semiconductor device of claim 15 , wherein the top surface of the lower work-function metal layer on which the RMG inner spacer is formed is lower than a level of a top surface of the lower gate metal pattern.
17 . The multi-stack semiconductor device of claim 16 , wherein the RMG inner spacer contacts at least one of the lower gate dielectric layer and the upper gate dielectric layer along a channel-length direction.
18 . The multi-stack semiconductor device of claim 17 , wherein at least the lower field-effect transistor is a nanosheet transistor, and the lower channel structure comprises a plurality of nanosheet layers vertically stacked on the substrate.
19 . The multi-stack semiconductor device of claim 15 , wherein the RMG inner spacer is formed in a groove which is formed on the lower work-function metal layer at the side of the lower gate metal pattern in the channel-width direction, and extended in a channel-length direction.
20 . The multi-stack semiconductor device of claim 15 , wherein the RMG inner spacer contacts a side surface of a portion of the lower gate metal pattern along a channel-length direction.