Semiconductor memory device and method for manufacturing the same
A semiconductor memory device includes a first dielectric wall, a second dielectric wall, first channel portions, second channel portions, an isolation wall, and a dielectric feature. The second dielectric wall is spaced apart from the first dielectric wall in a first direction. The first channel portions are disposed on a side of the first dielectric wall and are spaced apart from each other in a second direction transverse to the first direction. The second channel portions are disposed on a side of the second dielectric wall and are spaced apart from each other in the second direction. The isolation wall is located between the first dielectric wall and the second dielectric wall. The dielectric feature is disposed to separate the first dielectric wall and the isolation wall, and is disposed on the other side of the first dielectric wall opposite to the first channel portions in the first direction.
1 . A method for manufacturing a semiconductor memory device, comprising:
forming a plurality of fin-shaped structures that are spaced apart from each other in a first direction;
forming a plurality of dielectric walls that are spaced apart from each other in the first direction, each of the plurality of dielectric walls being located between corresponding two adjacent ones of the plurality of fin-shaped structures;
forming a plurality of isolation walls that are spaced apart from each other in the first direction, each of the plurality of isolation walls being located between corresponding two adjacent ones of the plurality of dielectric walls and being separated from the corresponding two adjacent ones of the plurality of dielectric walls respectively by corresponding two of the plurality of fin-shaped structures;
forming a mask layer to cover the plurality of fin-shaped structures, the plurality of dielectric walls and the plurality of isolation walls in a second direction transverse to the first direction;
patterning the mask layer to form a first through hole that penetrates the mask layer and that extends into a corresponding one of the plurality of dielectric walls, so as to expose a portion of a corresponding one of the plurality of isolation walls, a portion of a corresponding one of the plurality of fin-shaped structures that is adjacent to the corresponding one of the plurality of isolation walls, and the portion of a corresponding one of the plurality of dielectric walls that is separated from the corresponding one of the plurality of isolation walls by the corresponding one of the plurality of fin-shaped structures;
etching the corresponding one of the plurality of fin-shaped structures to form a second through hole; and
forming a dielectric layer to fill the second through hole, so as to form a dielectric feature in the second through hole.
2 . The method of claim 1 , wherein patterning the mask layer and etching the corresponding one of the plurality of fin-shaped structures are each conducted by a gas plasma etching process.
3 . The method of claim 2 , wherein, in the gas plasma etching process, a plasma generation power ranges from 500 W to 900 W.
4 . The method of claim 2 , wherein, in the gas plasma etching process, a gas plasma includes sulfur oxide (SO x ), fluorinated hydrocarbon (CH x F y ), or argon (Ar).
5 . The method of claim 2 , wherein, in the gas plasma etching process, a gas flow rate ranges from 10 sccm to 500 sccm.
6 . The method of claim 1 , wherein the dielectric feature includes an oxide-based material, silicon nitride, silicon carbonitride, silicon oxycarbonitride, or silicon oxycarbide.
7 . The method of claim 1 , wherein the dielectric feature has a height ranging from 50 nm to 150 nm.
8 . The method of claim 1 , after formation of a dielectric layer to fill the second through hole, further comprising simultaneously etching the corresponding one of the plurality of isolation walls and the dielectric feature.
9 . The method of claim 8 , wherein the etched dielectric feature has a width ranging from 10 nm to 100 nm, and has a height ranging from 10 nm to 100 nm.
10 . The method of claim 1 , wherein each of the plurality of fin-shaped structures includes a plurality of sacrificial layers and a plurality of channel layers which are alternately stacked on a semiconductor substrate in the second direction, each of the plurality of sacrificial layers including silicon germanium, each of the plurality of channel layers including silicon.
11 . A method for manufacturing a semiconductor memory device, comprising:
forming a plurality of fin-shaped structures on a plurality of upper portions of a substrate, respectively, the plurality of fin-shaped structures being spaced apart from each other;
forming a plurality of dielectric walls on a lower portion of the substrate, the plurality of upper portions of the substrate being extended from the lower portion of the substrate, and being spaced apart from each other, each of the plurality of dielectric walls being located between corresponding two adjacent ones of the plurality of fin-shaped structures;
forming a plurality of isolation walls on the lower portion of the substrate, each of the plurality of isolation walls being located between corresponding two adjacent ones of the plurality of dielectric walls and being separated from the corresponding two adjacent ones of the plurality of dielectric walls respectively by corresponding two of the plurality of fin-shaped structures;
forming a mask structure to cover the plurality of fin-shaped structures, the plurality of dielectric walls and the plurality of isolation walls opposite to the substrate;
patterning the mask structure to form a first through hole that penetrates the mask structure to expose a portion of a corresponding one of the plurality of isolation walls, a portion of a corresponding one of the plurality of fin-shaped structures that is adjacent to the corresponding one of the plurality of isolation walls, and a portion of a corresponding one of the plurality of dielectric walls that is separated from the corresponding one of the plurality of isolation walls by the corresponding one of the plurality of fin-shaped structures;
etching a part of the portion of the corresponding one of the plurality of fin-shaped structures to form a second through hole that extends into the corresponding one of the plurality of fin-shaped structures; and
forming a dielectric layer to fill the second through hole, so as to form a dielectric feature in the second through hole.
12 . The method of claim 11 , wherein the mask structure includes a lower mask layer, a middle mask layer, and an upper mask layer that are sequentially disposed on the plurality of fin-shaped structures, the plurality of dielectric walls and the plurality of isolation walls, and that are made of organosilicate-based material.
13 . The method of claim 12 , wherein the lower mask layer, the middle mask layer, and the upper mask layer have different silicon concentrations.
14 . The method of claim 12 , wherein the silicon concentration of the middle mask layer is greater than the silicon concentration of each of the lower mask layer and the upper mask layer.
15 . A method for manufacturing a semiconductor memory device, comprising:
forming a plurality of fin-shaped structures that are spaced apart from each other in a first direction;
forming a plurality of dielectric walls that are spaced apart from each other in the first direction, each of the plurality of dielectric walls being located between corresponding two adjacent ones of the plurality of fin-shaped structures;
forming a plurality of isolation walls that are spaced apart from each other in the first direction, each of the plurality of isolation walls being located between corresponding two adjacent ones of the plurality of dielectric walls and being separated from the corresponding two adjacent ones of the plurality of dielectric walls respectively by corresponding two of the plurality of fin-shaped structures;
forming a mask layer to cover the plurality of fin-shaped structures, the plurality of dielectric walls, and the plurality of isolation walls in a second direction transverse to the first direction;
patterning the mask layer to form a first through hole that penetrates the mask layer to expose a portion of a corresponding one of the plurality of isolation walls, a portion of a corresponding one of the plurality of fin-shaped structures that is adjacent to the corresponding one of the plurality of isolation walls, and a portion of a corresponding one of the plurality of dielectric walls that is separated from the corresponding one of the plurality of isolation walls by the corresponding one of the plurality of fin-shaped structures;
etching the corresponding one of the plurality of fin-shaped structures to form a second through hole, a bottom of the second through hole being located at a level lower than a level of an upper surface of the portion of the corresponding one of the plurality of dielectric walls;
forming a dielectric layer to fill the second through hole, so as to form a dielectric feature in the second through hole; and
removing the mask layer.
16 . The method of claim 15 , further comprising, after formation of the plurality of fin-shaped structures and before formation of the plurality of dielectric walls, forming a plurality of liner layers that surround the plurality of dielectric walls, respectively.
17 . The method of claim 16 , wherein a portion of a corresponding one of the plurality of liner layers that is separated from the corresponding one of the plurality of isolation walls by the corresponding one of the plurality of fin-shaped structures is exposed from the first through hole.
18 . The method of claim 16 , wherein each of the plurality of liner layers includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or combinations thereof.
19 . The method of claim 1 , wherein the first through hole further extends into the corresponding one of the plurality of isolation walls, so as to expose the portion of the corresponding one of the plurality of isolation walls.
20 . The method of claim 11 , wherein the dielectric feature extends into the corresponding one of the plurality of fin-shaped structures.