Three-dimensional cross field effect self-aligned transistors with frontside and backside power connections
An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit uses Cross field effect transistors (FETs) with a first device, such as n-type device, having a first channel oriented in a first direction and connected to a ground reference voltage level provided by a backside metal layer. The Cross FETs also use a second device, such as the p-type device, having a second channel oriented in a second direction orthogonal to the first direction and connected to a power supply reference voltage level provided by a frontside metal layer. A micro through silicon via (TSV) traverses the silicon substrate layer in order to be placed between the backside metal layer and the source region of an n-type device. The power connections reduce on-die area, reduces semiconductor fabrication complexity, which improves wafer yield, and reduces voltage droop, which increases performance.
1 . An integrated circuit comprising:
a first transistor comprising a first channel oriented in a first direction;
an oxide layer adjacent to the first transistor;
a second transistor adjacent to the oxide layer, wherein the second transistor comprises a second channel that is oriented in a direction orthogonal to the first direction; and
a backside power metal layer below a silicon substrate of the integrated circuit, wherein the backside metal layer forms a first power rail, is connected to the second transistor, and is configured to route a first voltage reference level of the first power rail.
2 . The integrated circuit as recited in claim 1 , further comprising a frontside metal layer that forms a second power rail, is connected to the first transistor, and is configured to route a second voltage reference level of the second power rail.
3 . The integrated circuit as recited in claim 2 , wherein a first doping polarity of the first channel is an opposite polarity of a second doping polarity of the second channel.
4 . The integrated circuit as recited in claim 2 , wherein the first voltage reference level is different from the second voltage reference level.
5 . The integrated circuit as recited in claim 2 , further comprising a micro through silicon via (TSV) that traverses through the silicon substrate between a source region of the second transistor and the backside metal layer.
6 . The integrated circuit as recited in claim 2 , further comprising a heat sink located nearer a plurality of backside metal layers than a plurality of frontside metal layers.
7 . The integrated circuit as recited in claim 6 , further comprising a copper barrier adhesion layer between the plurality of backside metal layers and a carrier wafer.
8 . A method comprising:
forming, in an integrated circuit, a first transistor with a first channel oriented in a first direction;
forming, in the integrated circuit, an oxide layer adjacent to the first transistor;
forming, in the integrated circuit, a second transistor adjacent to the oxide layer, wherein the second transistor comprises a second channel that is oriented in a direction orthogonal to the first direction; and
forming a backside metal layer below a silicon substrate of the integrated circuit, wherein the backside metal layer forms a first power rail, is connected to the second transistor, and is configured to route a first voltage reference level of the first power rail.
9 . The method as recited in claim 8 , further comprising forming a frontside metal layer that forms a second power rail, is connected to the first transistor, and routes a second voltage reference level of the second power rail.
10 . The method as recited in claim 9 , further comprising forming the first channel with a first doping polarity that is an opposite polarity of a second doping polarity of the second channel.
11 . The method as recited in claim 9 , wherein the first voltage reference level is different from the second voltage reference level.
12 . The method as recited in claim 9 , further comprising forming a micro through silicon via (TSV) that traverses through the silicon substrate layer between a source region of the second transistor and the backside metal layer.
13 . The method as recited in claim 9 , further comprising forming a heat sink located nearer a plurality of backside metal layers than a plurality of frontside metal layers.
14 . The method as recited in claim 13 , further comprising forming a copper barrier adhesion layer between the plurality of backside metal layers and a carrier wafer.
15 . A computing system comprising:
a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks;
an integrated circuit configured to execute the instructions of the one or more tasks using the source data, wherein the integrated circuit comprises:
a first transistor comprising a first channel oriented in a first direction;
an oxide layer adjacent to the first transistor;
a second transistor adjacent to the oxide layer, wherein the second transistor comprises a second channel that is oriented in a direction orthogonal to the first direction; and
a backside metal layer below a silicon substrate of the integrated circuit, wherein the backside metal layer forms a first power rail, is connected to the second transistor, and is configured to route a first voltage reference level of the first power rail.
16 . The computing system as recited in claim 15 , wherein the integrated circuit further comprises a frontside metal layer that forms a second power rail, is connected to the first transistor, and is configured to route a second voltage reference level of the second power rail.
17 . The computing system as recited in claim 16 , wherein a first doping polarity of the first channel is an opposite polarity of a second doping polarity of the second channel.
18 . The computing system as recited in claim 16 , wherein the first voltage reference level is different from the second voltage reference level.
19 . The computing system as recited in claim 16 , wherein the integrated circuit further comprises a micro through silicon via (TSV) that traverses through the silicon substrate between a source region of the second transistor and the backside metal layer.
20 . The computing system as recited in claim 16 , wherein the integrated circuit further comprises a heat sink located nearer a plurality of backside metal layers than a plurality of frontside metal layers.