Semiconductor device with polymer liner and method for fabricating the same
The present disclosure provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a first substrate, having a front side and a back side opposite to the front side; a first passivation layer over the front side of the first substrate; a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate; a conductive feature disposed in the first passivation layer; a through substrate via penetrating through the second passivation layer and the first substrate; and a polymer liner between a sidewall of the through substrate via and the first substrate.
1. A semiconductor device, comprising:
a first substrate, having a front side and a back side opposite to the front side;
a first passivation layer over the front side of the first substrate;
a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate;
a conductive feature disposed in the first passivation layer, wherein the conductive feature comprises a conductive pad and an interconnect structure electrically connected to the conductive pad;
a through substrate via (TSV) penetrating through the second passivation layer and the first substrate, wherein the TSV is electrically coupled to the conductive feature;
a polymer liner between a sidewall of the TSV and the first substrate, wherein a top surface of the polymer liner is lower than the top surface of the second passivation layer; and
an isolation liner between the polymer liner and the first substrate.
2. The semiconductor device of claim 1 , further comprising a barrier layer between the polymer liner and the TSV.
3. The semiconductor device of claim 1 , wherein the polymer liner comprises fluoride-based polymer material.
4. The semiconductor device of claim 3 , wherein a dielectric constant of the polymer liner is less than 3.5.
5. The semiconductor device of claim 1 , wherein the polymer liner comprises:
a first portion laterally surrounded by the second passivation layer; and
a second portion laterally surrounded by the first substrate.
6. The semiconductor device of claim 1 , wherein a sidewall of the first substrate comprises a recessed portion proximal to the second passivation layer.
7. The semiconductor device of claim 1 , wherein the isolation liner comprises oxide or nitride.
8. The semiconductor structure of claim 1 , wherein the top surface of the polymer liner is lower than a top surface of the isolation liner.
9. The semiconductor device of claim 1 , wherein the polymer liner is in direct contact with the interconnect structure.