Semiconductor device with polymer liner and method for fabricating the same
The present disclosure provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a first substrate, having a front side and a back side opposite to the front side; a first passivation layer over the front side of the first substrate; a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate; a conductive feature disposed in the first passivation layer; a through substrate via penetrating through the second passivation layer and the first substrate; and a polymer liner between a sidewall of the through substrate via and the first substrate.
1 . A method of manufacturing a semiconductor device, comprising:
forming a conductive feature in a first passivation layer over a front side of a first substrate;
forming a second passivation layer over a back side of the first substrate;
forming a first recess in a top surface of the second passivation layer to expose the conductive feature;
performing a pulsed etching operation to form a polymer liner in the first recess, wherein a top surface of the polymer liner is lower than the top surface of the second passivation layer;
forming a conductive material in the first recess to form a through substrate via (TSV); and
coupling a second substrate to the first substrate.
2 . The method of claim 1 , further comprising:
forming an isolation liner in the first recess prior to forming the polymer liner.
3 . The method of claim 2 , wherein the isolation liner comprises oxide or nitride-based material.
4 . The method of claim 1 , wherein the performing of the pulsed etching operation comprises: supplying at least one of the following chemicals: C 4 F 8 , C 4 F 6 , and carbon monoxide.
5 . The method of claim 1 , wherein the performing of the pulsed etching operation comprises altering a bias power with a switching interval that is in a range between 10 −4 s and 10 s.
6 . The method of claim 1 , wherein the forming of the TSV comprises: performing a planarization operation over the conductive material.