Multi-threshold voltage integration scheme for semiconductor devices
Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and V t requirements (including multi-V t ), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on the top surface of the channel; depositing a hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 Å on the interfacial layer; and depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer.
1 . A method of manufacturing an electronic device, the method comprising:
forming a P-dipole stack and an N-dipole stack on a semiconductor substrate, each of the P-dipole stack and the N-dipole stack formed on a top surface of a channel located between a source and a drain on the semiconductor substrate, forming each of the P-dipole stack and the N-dipole stack comprising sequentially:
depositing an interfacial layer on the top surface of the channel;
depositing a hafnium-containing layer on the interfacial layer, the hafnium-containing layer having a thickness of less than or equal to 5 Å;
depositing a dipole layer on the hafnium-containing layer;
selectively etching the dipole layer from one of the P-dipole stack or the N-dipole stack and increasing a thickness of the dipole layer on the other of the P-dipole stack or the N-dipole stack to form multiple threshold voltages (multi-V t ); and
depositing a high-κ dielectric layer having a thickness in a range of from 10 Å to 20 Å on the dipole layer.
2 . The method of claim 1 , wherein the interfacial layer comprises a silicon oxide (SiOx) layer formed on doped silicon or undoped silicon.
3 . The method of claim 1 , wherein the hafnium-containing layer comprises one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), nitrogen-doped hafnium oxide (HfOx), or nitrogen-doped hafnium zirconium oxide (HfZrOx).
4 . The method of claim 1 , wherein the hafnium-containing layer has a thickness of less than or equal to 3 Å.
5 . The method of claim 1 , wherein the high-κ dielectric layer comprises one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).
6 . The method of claim 1 , wherein depositing the dipole layer comprises exposing the semiconductor substrate to a pulse of a metal-containing precursor and a pulse of a reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.
7 . The method of claim 6 , wherein the metal-containing comprises one or more of titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), germanium (Ge), gallium (Ga), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), or boron (B).
8 . The method of claim 6 , wherein the reactant comprises ammonia (NH 3 ).
9 . The method of claim 6 , wherein the dipole layer comprises lanthanum nitride (LaN) or aluminum nitride (AlN).
10 . The method of claim 1 , further comprising annealing the P-dipole stack and the N-dipole stack at a temperature of less than or equal to 1000° C. to drive in metal atoms from the dipole layer and densify the high-κ dielectric layer to form an annealed high-κ dielectric layer.
11 . The method of claim 10 , further comprising depositing a work-function layer on the annealed high-κ dielectric layer.
12 . The method of claim 1 , wherein the method improves a threshold voltage (V t ) of the electronic device compared to a method that does not include forming a hafnium-containing layer having a thickness of less than or equal to 5 Å on the interfacial layer.
13 . The method of claim 1 , wherein the method reduces leakage (J g ) of the electronic device compared to a method that does not include forming a hafnium-containing layer having a thickness of less than or equal to 5 Å on the interfacial layer.
14 . A method of manufacturing an electronic device, the method comprising:
forming a P-dipole stack and an N-dipole stack on a semiconductor substrate, each of the P-dipole stack and the N-dipole stack formed on a top surface of a channel located between a source and a drain on the semiconductor substrate, forming each of the P-dipole stack and the N-dipole stack comprising sequentially:
depositing an interfacial layer on the top surface of the channel, the interfacial layer comprising silicon oxide (SiOx);
depositing a hafnium-containing layer on the interfacial layer, the hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 Å;
depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer;
selectively etching the dipole layer from one of the P-dipole stack or the N-dipole stack and increasing a thickness of the dipole layer on the other of the P-dipole stack or the N-dipole stack to form multiple threshold voltages (multi-V t ); and
depositing a high-κ dielectric layer having a thickness in a range of from 10 Å to 20 Å on the dipole layer.
15 . The method of claim 14 , wherein the high-κ dielectric layer comprises one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).
16 . The method of claim 14 , further comprising annealing the P-dipole stack and the N-dipole stack at a temperature of less than or equal to 1000° C. to drive in metal atoms from the dipole layer and densify the high-κ dielectric layer to form an annealed high-κ dielectric layer.
17 . The method of claim 16 , further comprising depositing a work-function layer on the annealed high-κ dielectric layer.
18 . The method of claim 14 , wherein the method reduces leakage (J g ) of the electronic device compared to a method that does not include forming a hafnium-containing layer having a thickness of less than or equal to 5 Å on the interfacial layer.