Systems and methods for non-overlap enforcement for inverter for electric vehicle
A system includes: an inverter including: a first galvanic interface to separate a first high voltage area from a low voltage area; a first low voltage controller in the low voltage area, the first low voltage controller configured to send a first control signal using the first galvanic interface to a first high voltage controller in the first high voltage area; a second galvanic interface to separate a second high voltage area from the low voltage area; and a second low voltage controller in the low voltage area, the first low voltage controller configured to send a second control signal using the second galvanic interface to a second high voltage controller in the second high voltage area, wherein the second low voltage controller is configured to provide an output latch signal to the first low voltage controller and receive an input latch signal from the first low voltage controller.
1. A system comprising:
an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes:
a first galvanic interface configured to separate a first high voltage area from a low voltage area;
a first low voltage controller in the low voltage area, the first low voltage controller configured to receive a first PWM signal from a PWM controller, and send a first control signal using the first galvanic interface to a first high voltage controller in the first high voltage area based on the first PWM signal;
a second galvanic interface configured to separate a second high voltage area from the low voltage area; and
a second low voltage controller in the low voltage area, the first low voltage controller configured to receive a second PWM signal from the PWM controller, and send a second control signal using the second galvanic interface to a second high voltage controller in the second high voltage area based on the second PWM signal,
wherein the second low voltage controller is configured to provide an output latch signal to the first low voltage controller and receive an input latch signal from the first low voltage controller, and
wherein the output latch signal is based on the second PWM signal and the input latch signal.
2. The system of claim 1 ,
wherein the first low voltage controller is further configured to receive a feedback signal over the first galvanic interface from the first high voltage controller, and
wherein the input latch signal is based on the first PWM signal, the output latch signal, and the feedback signal.
3. The system of claim 2 ,
wherein the first low voltage controller is configured to send the first control signal using a set of communication lines of the first galvanic interface and receive the feedback signal using the set of communication lines in the first galvanic interface.
4. The system of claim 2 , wherein the first control signal is configured to control a phase switch of an inverter, and the feedback signal is configured to indicate an off-state of the phase switch.
5. The system of claim 2 , wherein the first low voltage controller is configured to record a time based on the first PWM signal and the feedback signal.
6. The system of claim 1 , wherein the first low voltage controller is configured to generate a fault based on the first PWM signal and the output latch signal.
7. The system of claim 1 , wherein the output latch signal and the input latch signal enable the first PWM signal in the first low voltage controller and the second PWM signal in the second low voltage controller, respectively.
8. The system of claim 1 , further comprising:
the battery configured to supply the DC power to the inverter; and
the motor configured to receive the AC power from the inverter to drive the motor.
9. A system comprising:
a high voltage controller configured to be in a high voltage area separated from a low voltage area by a galvanic interface including a command channel and a message channel, the high voltage controller configured to receive a control signal from a low voltage controller in the low voltage area using the command channel of the galvanic interface, control a phase switch based on the control signal, and send a switch state signal to the low voltage controller using the command channel of the galvanic interface,
wherein the high voltage controller is configured to control the switch state signal based on a state of the phase switch.
10. The system of claim 9 , wherein the high voltage controller is configured to send the switch state signal using the command channel of the galvanic interface when the high voltage controller is not receiving the control signal from the command channel of the galvanic interface.
11. The system of claim 9 , wherein the high voltage controller is configured to send the switch state signal by sending a burst of galvanic pulses on the command channel of the galvanic interface.
12. The system of claim 9 , wherein the high voltage controller includes one or more point-of-use controllers on a power module with the phase switch.
13. The system of claim 9 , wherein the high voltage controller is configured to send the control signal to one or more point-of-use controllers on a power module with the phase switch, and receive the switch state signal from the one or more point-of-use controllers.
14. The system of claim 9 , wherein the high voltage controller is further configured to invert the switch state signal, and send the switch state signal and the inverted switch state signal to the low voltage controller using the command channel of the galvanic interface.
15. A system including:
a galvanic interface configured to separate a high voltage area from a low voltage area;
a low voltage controller in the low voltage area, the low voltage controller including:
a PWM comparator configured to receive a PWM signal and an input latch signal, and generate a PWM comparator signal based on a comparison of the PWM signal and the input latch signal,
a low voltage pulse generator configured to generate an upstream pulse based on the PWM comparator signal,
a low voltage transmitter configured to send the upstream pulse to the galvanic interface,
a low voltage receiver configured to receive a downstream pulse from the galvanic interface,
a low voltage demodulator configured to generate a low voltage demodulated signal based on the downstream pulse, and
an enable latch configured to be set with the low voltage demodulated signal and to be reset with the PWM comparator signal, the enable latch further configured to provide an output latch signal; and
a high voltage controller in the high voltage area, the high voltage controller including:
a high voltage receiver configured to receive the upstream pulse from the galvanic interface,
a high voltage demodulator configured to generate a high voltage demodulated signal based on the upstream pulse, the high voltage demodulated signal configured to control a phase switch,
a high voltage off-state detector configured to detect an off-state of the phase switch,
a high voltage pulse generator configured to generate the downstream pulse based on the detected off-state of the phase switch, and
a high voltage transmitter configured to send the downstream pulse to the galvanic interface.
16. The system of claim 15 , wherein the high voltage controller includes one or more point-of-use controllers on a power module with the phase switch.
17. The system of claim 15 , wherein the low voltage controller further includes:
a roundtrip timer configured to record a time from when the PWM signal changes to a logic low to when the output latch signal changes to a logic high.
18. The system of claim 15 , wherein the low voltage controller further includes:
an overlap comparator configured to generate a fault when the PWM signal is a logic high and the input latch signal is a logic low.
19. The system of claim 15 , wherein the high voltage controller further includes:
a high voltage inverter configured to invert the downstream pulse to the high voltage transmitter.
20. The system of claim 15 , wherein the low voltage controller further includes:
a low voltage inverter configured to invert the upstream pulse to the low voltage transmitter.