Signal processing apparatus for use in optical communication
A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters. The signal processing apparatus further includes a digital pre-processing stage that receives the one or more distortion compensation parameters from the digital compensation engine and performs distortion compensation pre-processing on the digital input signal.
1. A signal processing apparatus, comprising:
a plurality of time-interleaving digital-to-analog converters (sub-DACs), each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal;
an analog multiplexer configured to sample the plurality of sub-DAC output signals at a preset multiplexer clock frequency, and to generate a multiplexer output signal;
a local analog-to-digital converter (ADC), configured to receive the multiplexer output signal and generate a digital feedback signal;
a digital compensation engine configured to receive the digital feedback signal from the local ADC and determine one or more distortion compensation parameters based on a comparison of the digital feedback signal with the digital input signal; and
a digital pre-processing stage configured to receive the one or more distortion compensation parameters from the digital compensation engine and perform distortion compensation pre-processing on the digital input signal.
2. The signal processing apparatus of claim 1 , wherein the digital pre-processing stage is configured to perform the distortion compensation pre-processing online.
3. The signal processing apparatus of claim 1 , wherein the distortion compensation parameters include one or more sub-DAC sample frequency parameters.
4. The signal processing apparatus of claim 3 , further comprising a sub-DAC time-delay controller, configured to receive the one or more sub-DAC sample frequency parameters, and to adjust a respective time-delay for each sub-DAC.
5. The signal processing apparatus of claim 1 , wherein the distortion compensation parameters include one or more sub-DAC non-linearity parameters, and the digital compensation engine is configured to determine the sub-DAC non-linearity parameters based on parameters of a memory-less spline digital pre-distorter model.
6. The signal processing apparatus of claim 4 , wherein the distortion compensation parameters include one or more sub-DAC gain parameters.
7. The signal processing apparatus of claim 6 , wherein the distortion compensation parameters include one or more sub-DAC voltage offset parameters.
8. The signal processing apparatus of claim 7 , further comprising:
a single tone generator configured to output a single frequency sample tone to the digital pre-processing stage; and
a power detector configured to receive the multiplexer output signal and generate a power feedback signal;
wherein the digital compensation engine is configured to receive the power feedback signal from the power detector and determine one or more of the sub-DAC voltage offset parameters based on a comparison of the power feedback signal with the single frequency sample tone.
9. The signal processing apparatus of claim 8 , wherein the single tone generator is configured to output the single frequency sample tone while the digital input signal is not input to the digital pre-processing stage.
10. The signal processing apparatus of claim 9 , further comprising
a sub-DAC voltage controller, configured to receive the one or more sub-DAC gain parameters and/or sub-DAC voltage offset parameters, and to adjust a respective gain and/or voltage offset for each sub-DAC.
11. The signal processing apparatus of claim 1 , wherein the local ADC is configured to sample the multiplexer output signal at a preset sampling frequency which is substantially smaller than the multiplexer clock frequency.
12. The signal processing apparatus of claim 1 , further comprising:
a pseudorandom noise generator configured to generate noise in an out-of-band region of the digital input signal.