IP Library › Granted Patent US 12,740,454
Granted Patent B2
US 12,740,454 · App. 18/194,702 · Granted Sep 15, 2026

Microelectronic assemblies with direct bonding using nanotwinned copper

Inventors: Vivek Chidambaram (Singapore, SG); Jonathan Burk (Portland, OR); Zhihua Zou (Chandler, AZ)
Assignee: Intel Corporation
H10W70/685H10W70/611H10W90/00H10W72/07253H10W72/237H10W72/252H10W72/257H10W74/00H10W74/15H10W90/722H10W90/724H10W90/732H10W90/734
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,740,454
App. No.
18/194,702
Granted
Sep 15, 2026
Kind
B2
Abstract

Disclosed herein are microelectronic assemblies with direct bonding using nanotwinned copper (NTC). An example microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding (DB) region, wherein the DB region includes a DB contact comprising a first portion and a second portion having different microstructures. The first portion is between the first microelectronic component and the second portion. The second portion is between the first portion and the second microelectronic component. In some implementations, the first portion has non-columnar microstructure, and the second portion has columnar microstructure. In some implementations, less than about 40% of grains of the first portion have ac <111> orientation, and at least about 50% of grains of the second portion have the <111> orientation. In some embodiments, the first portion includes PCC or FGC, and the second portion includes NTC.

Claims (36)

1 . A microelectronic assembly, comprising:

a first microelectronic component; and

a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a direct bonding contact comprising a first portion and a second portion, the first portion is between the first microelectronic component and the second portion, and the first portion and the second portion have different microstructures.

2 . The microelectronic assembly according to claim 1 , wherein the first portion and the second portion having different microstructures includes the first portion and the second portion having different grain orientations.

3 . The microelectronic assembly according to claim 1 , wherein at least about 50% of grains of the second portion have a <111> orientation, and less than about 40% of grains of the first portion have the <111> orientation.

4 . The microelectronic assembly according to claim 1 , wherein grains of the first portion have substantially random orientation.

5 . The microelectronic assembly according to claim 1 , wherein the second portion has a columnar microstructure and the first portion has a non-columnar microstructure.

6 . The microelectronic assembly according to claim 1 , wherein the first portion and the second portion having different microstructures includes the first portion and the second portion having different average grain dimensions.

7 . The microelectronic assembly according to claim 1 , wherein an average grain length of grains in the second portion is at least about 1 micron and wherein an average grain width of grains in the second portion is at least 20% smaller than the average grain length.

8 . The microelectronic assembly according to claim 1 , wherein the second portion includes nanotwinned copper, and wherein the first portion includes an electrically conductive material other than the nanotwinned copper.

9 . The microelectronic assembly according to claim 1 , wherein a thickness of the first portion is at least about 400 nanometers and wherein a thickness of the second portion is less than about 300 nanometers.

10 . The microelectronic assembly according to claim 1 , wherein the direct bonding contact further includes a third portion, the second portion is between the first portion and the third portion, and the first portion and the third portion have substantially same microstructures.

11 . The microelectronic assembly according to claim 1 , wherein the direct bonding contact further includes a third portion, the second portion is between the first portion and the third portion, and the second portion and the third portion have different microstructures.

12 . The microelectronic assembly according to claim 1 , wherein the direct bonding region further includes a direct bonding dielectric comprising a first portion and a second portion, the first portion of the direct bonding dielectric is between the first microelectronic component and the second portion of the direct bonding dielectric, and an atomic percentage of carbon in the first portion of the direct bonding dielectric is lower than an atomic percentage of carbon in the second portion of the direct bonding dielectric.

13 . The microelectronic assembly according to claim 12 , wherein the atomic percentage of carbon in the first portion of the direct bonding dielectric is below 25%, and wherein the atomic percentage of carbon in the second portion of the direct bonding dielectric is above 25%.

14 . The microelectronic assembly according to claim 12 , wherein a thickness of the first portion of the direct bonding dielectric is at least 300 nanometers and wherein a thickness of the second portion of the direct bonding dielectric is less than 300 nanometers.

15 . The microelectronic assembly according to claim 12 , wherein the direct bonding dielectric further includes silicon and nitrogen.

16 . The microelectronic assembly according to claim 1 , wherein the first microelectronic component is a die and the second microelectronic component is one of a further die, an interposer, a package substrate, or a circuit board.

17 . A microelectronic assembly, comprising:

a first microelectronic component; and

a second microelectronic component coupled to the first microelectronic component by a direct bonding contact,

wherein the direct bonding contact includes a first portion and a second portion, the first portion is between the first microelectronic component and the second portion, less than about 40% of grains of the first portion have a <111> orientation, and at least about 50% of grains of the second portion have the <111> orientation.

18 . The microelectronic assembly according to claim 17 , further comprising a direct bonding dielectric between the first microelectronic component and the second microelectronic component, wherein:

the direct bonding dielectric encloses sidewalls of the direct bonding contact,

the direct bonding dielectric includes a first portion and a second portion,

the first portion of the direct bonding dielectric is between the first microelectronic component and the second portion of the direct bonding dielectric, and

an atomic percentage of carbon in the first portion of the direct bonding dielectric is lower than an atomic percentage of carbon in the second portion of the direct bonding dielectric.

19 . A microelectronic assembly, comprising:

a first microelectronic component; and

a second microelectronic component coupled to the first microelectronic component by a direct bonding contact,

wherein the direct bonding contact includes a first portion and a second portion, the first portion is between the first microelectronic component and the second portion, the first portion includes polycrystalline copper or fine-grained copper, and the second portion includes nanotwinned copper.

20 . The microelectronic assembly according to claim 19 , further comprising a direct bonding dielectric between the first microelectronic component and the second microelectronic component, wherein:

the direct bonding dielectric encloses sidewalls of the direct bonding contact,

the direct bonding dielectric includes a first portion and a second portion,

the first portion of the direct bonding dielectric is between the first microelectronic component and the second portion of the direct bonding dielectric, and

an atomic percentage of carbon in the first portion of the direct bonding dielectric is lower than an atomic percentage of carbon in the second portion of the direct bonding dielectric.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076007/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2023
From: CHIDAMBARAM, VIVEK; BURK, JONATHAN; ZOU, ZHIHUA
To: INTEL CORPORATION
Reel/Frame 063240/0723 →
Continuity (1)
Related Publication 20240332237A1 · Oct 3, 2024
References Cited (36)
US 20120135260A1 · Jang · 2012 [cited by examiner]
US 20120252189A1 · Sadaka · 2012 [cited by examiner]
US 20130249532A1 · Lin et al. · 2013 [cited by applicant]
US 20150270209A1 · Woychik et al. · 2015 [cited by applicant]
US 20160190103A1 · Kabe et al. · 2016 [cited by applicant]
US 20190109042A1 · Katkar et al. · 2019 [cited by applicant]
US 20190123006A1 · Chen et al. · 2019 [cited by applicant]
US 20190385977A1 · Elsherbini et al. · 2019 [cited by applicant]
US 20200126906A1 · Uzoh et al. · 2020 [cited by applicant]
US 20200266156A1 · Lee · 2020 [cited by applicant]
US 20200279813A1 · Liff et al. · 2020 [cited by applicant]
US 20220093492A1 · Elsherbini et al. · 2022 [cited by applicant]
US 20220093561A1 · Eid et al. · 2022 [cited by applicant]
US 20220093725A1 · Elsherbini et al. · 2022 [cited by applicant]
US 20220102305A1 · Krishnatreya et al. · 2022 [cited by applicant]
US 20230132632A1 · Katkar · 2023 [cited by examiner]
US 20230307392A1 · Lu · 2023 [cited by examiner]
DE 102019115275A1 · 2020 [cited by applicant]
EP 1490903B1 · 2015 [cited by applicant]
EP 3594994A1 · 2020 [cited by applicant]
WO 2019132960A1 · 2019 [cited by applicant]
WO 2019132961A1 · 2019 [cited by applicant]
“Capacitor”, Wikipedia, Jun. 6, 2020, Retrieved from the internet on 202-Feb. 17, https://en.wikipedia.org/w/index.php?title=Capacitory&oldid-96098607. [cited by applicant]
Chidambarim, Vivek et al “Au-in-based Hermetic Sealing for MEMS Packaging for Down-Hole Application,” Journal of Electronic Materials, Published online : Apr. 8, 2014, 12 pages. [cited by applicant]
Han, Tiancheng et al., “Manipulating Steady Heat Conduction by Sensu-shaped Thermal Metamaterials,” Scientific Reports, May 14, 2005, 7 pages. [cited by applicant]
Jani, Imed et al “BISTs for Post-Bond Test and Electrical Analysis of High Density 3D Interconnect defect”, 2018 23rd IEEE European Test Symposium (ETS), 6 pages. [cited by applicant]
Li, Sujie et al “Nano-scale twinned Cu with ultrahigh strength prepared by direct current electrodeposition,” Materials Science & engineering A 758 (2019) 1-6. [cited by applicant]
Mirkarimi, Laurat et al “The Influence of Cu Microstructure on Thermal Budget in Hybrid Bonding,” 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) retrieved from the internet on Jan. 7, 2023, pp. 16… [cited by applicant]
Sun, Fu-Long et al “Bottom-Up Electrodeposition of Large-Scale Nanotwinned Copper with in 3D Through Silicon Via,” Materials, 2018, 11, 319; doi: 10.3390/ma11020319, retrieved from mdpi.com/journal/materials, 7 pages. [cited by applicant]
Chidambaram, Vivek et al “A comparative assessment of die to wafer hybrid bonding process flow against mature wafer to wafer hybrid bonding process flow”, Intel Assembly & Test Technology Journal (IATTJ), vol. 25, 2022,… [cited by applicant]
Chidambaram, Vivek et al, U.S. Appl. No. 18/194,702, filed Apr. 3, 2024 entitled “Microelectronic Assemblies with Direct Bonding using Nanotwinned Copper”, Inventors Vivek Chidambaram et al, 44 pages. [cited by applicant]
Fowler, Shelly, “Material Solutions For FOWLP Die Shift And Wafer Warpage” Material Solutions For FOWLP Die Shift And Wafer Warpage, Jun. 20, 2019, retrieved on Mar. 31, 2024 from https://semiengineering.com/material-so… [cited by applicant]
Garrou, Phil “FTLE 443: Controlling Warpage and Placement FOWLP” Blogs, Packaging IFTLE, IFTLE 443: Controlling Warpage and Placement Error for FOWLP-3D InCites, retrieved on Mar. 31, 2024 https://www.3dincites.com/2020… [cited by applicant]
Iwai, Masahiro et al “Latest Technologies of Epoxy Molding Compound (EMC) for FO-WLP” 53rd International Symposium on Microelectronics, IMAPS 2020, Oct. 5-8, 2020, Virtual Symposium, pp. 000051-000056. [cited by applicant]
Suhard, Samuel et al “Demonstration of a collective hybrid die-to-wafer integration using glass carrier”, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp. 2064-2070. [cited by applicant]
Uhrmann, Thomas, et al “Heterogeneous Integration By Collective Die-To-Wafer Bonding”, Proceeding of the International Wafer-Level Packaging Conference 201, Retrieved on Mar. 31, 2024 from UTC from IEEE Xplore, 4 pages. [cited by applicant]