Fin stack including tensile-strained and compressively strained fin portions
A fin stack including compressively strained and tensile-strained semiconductor fin regions allows CMOS fabrication to form vertically stacked p-type FinFETs and n-type FinFETs. Aspect ratio trapping within a semiconductor base region within the fin stack provides a relaxed semiconductor base region on which uniaxially strained regions are grown. A dielectric layer may be formed to electrically isolate the compressively strained semiconductor fin region from the tensile-strained semiconductor fin region.
1. A method of fabricating a finned, monolithic semiconductor structure, comprising:
forming at least one trench within a dielectric layer and extending down to a semiconductor substrate layer;
epitaxially forming a bottom semiconductor base region within the at least one trench and adjoining the semiconductor substrate layer, wherein epitaxially forming the bottom semiconductor base region further includes trapping defects within the bottom semiconductor base region by aspect ratio trapping;
epitaxially forming a first semiconductor fin region within the at least one trench on the bottom semiconductor base region, the first semiconductor fin region having a first strain type; and
epitaxially forming a second semiconductor fin region within the at least one trench over the first semiconductor fin region, the second semiconductor fin region having a second strain type;
wherein the first strain type is different from the second strain type; and
wherein forming the first semiconductor fin region includes epitaxially growing a first semiconductor material on the bottom semiconductor base region and recessing the first semiconductor material within the at least one trench.
2. A method of fabricating a finned, monolithic semiconductor structure, comprising:
forming at least one trench within a dielectric layer and extending down to a semiconductor substrate layer;
epitaxially forming a bottom semiconductor base region within the at least one trench and adjoining the semiconductor substrate layer, wherein epitaxially forming the bottom semiconductor base region further includes trapping defects within the bottom semiconductor base region by aspect ratio trapping;
epitaxially forming a first semiconductor fin region within the at least one trench on the bottom semiconductor base region, the first semiconductor fin region having a first strain type; and
epitaxially forming a second semiconductor fin region within the at least one trench over the first semiconductor fin region, the second semiconductor fin region having a second strain type;
wherein the first strain type is different from the second strain type; and
wherein forming the first semiconductor fin region includes epitaxially growing a first semiconductor material on the bottom semiconductor base region and recessing the first semiconductor material within the at least one trench;
further including:
epitaxially forming a top semiconductor base region over the first semiconductor fin region; and
replacing the top semiconductor base region with an electrical insulator.
3. The method of claim 2 , wherein the bottom semiconductor base region comprises silicon germanium and the first semiconductor material includes a germanium concentration greater than the germanium concentration of the bottom semiconductor base region.
4. The method of claim 2 , further including:
forming a recess within the dielectric layer extending perpendicularly to and intersecting the at least one trench; and
forming a dielectric anchor structure within the recess, the first and second semiconductor fin regions including end portions adjoining the dielectric anchor structure.
5. The method of claim 4 , wherein the recess and the dielectric anchor structure extend into the semiconductor substrate layer.
6. A method of fabricating a finned, monolithic semiconductor structure, comprising:
forming at least one trench within a dielectric layer and extending down to a semiconductor substrate layer;
epitaxially forming a bottom semiconductor base region within the at least one trench and adjoining the semiconductor substrate layer, wherein epitaxially forming the bottom semiconductor base region further includes trapping defects within the bottom semiconductor base region by aspect ratio trapping;
epitaxially forming a first semiconductor fin region within the at least one trench on the bottom semiconductor base region, the first semiconductor fin region having a first strain type; and
epitaxially forming a second semiconductor fin region within the at least one trench over the first semiconductor fin region, the second semiconductor fin region having a second strain type;
wherein the first strain type is different from the second strain type;
further including:
forming a faceted top surface including {111} surface planes on the first semiconductor fin region; and
epitaxially growing a top semiconductor base region on the faceted top surface.
7. The method of claim 6 , wherein the second semiconductor fin region comprises a group III-V compound.
8. The method of claim 6 , wherein epitaxially forming the second semiconductor fin region includes growing a compound semiconductor material on the faceted top surface of the top semiconductor base region.
9. A method of fabricating a finned, monolithic semiconductor structure, comprising:
forming at least one trench within a dielectric layer and extending down to a semiconductor substrate layer;
epitaxially forming a bottom semiconductor base region within the at least one trench and adjoining the semiconductor substrate layer, wherein epitaxially forming the bottom semiconductor base region further includes trapping defects within the bottom semiconductor base region by aspect ratio trapping;
epitaxially forming a first semiconductor fin region within the at least one trench on the bottom semiconductor base region, the first semiconductor fin region having a first strain type; and
epitaxially forming a second semiconductor fin region within the at least one trench over the first semiconductor fin region, the second semiconductor fin region having a second strain type;
wherein the first strain type is different from the second strain type;
further including:
electrically isolating the second semiconductor fin region from the first semiconductor fin region; and
recessing the dielectric layer, thereby exposing the first semiconductor fin region and the second semiconductor fin region.