IP Library Granted Patent US 12,237,394
Granted Patent B2
US 12,237,394 · App. 18/226,262 · Granted Feb 25, 2025

Semiconductor device and method for fabricating the same

Inventors: Yi-Fan Li (Tainan, TW); Wen-Yen Huang (Changhua County, TW); Shih-Min Chou (Tainan, TW); Zhen Wu (Kaohsiung, TW); Nien-Ting Ho (Tainan, TW); Chih-Chiang Wu (Tainan, TW); Ti-Bin Chen (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/4966H01L27/092H01L29/401
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Quick Facts
Patent No.
US 12,237,394
App. No.
18/226,262
Granted
Feb 25, 2025
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Claims (21)

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a first region and a second region, wherein the first region comprises a PMOS region and the second region comprises a NMOS region;

forming a first bottom barrier metal (BBM) layer on the first region and the second region;

forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region;

forming a diffusion barrier layer on the first WFM layer; and

removing the diffusion barrier layer on the second region.

2. The method of claim 1 , further comprising:

forming a gate structure on the substrate on the first region and the second region;

forming an inter-layer dielectric (ILD) layer around the gate structure;

removing the gate structure to form a recess;

forming the first BBM layer in the recess;

forming the first WFM layer on the first BBM layer;

forming the diffusion barrier layer on the first WFM layer;

removing the diffusion barrier layer and the first WFM layer on the second region;

forming a second WFM layer on the diffusion barrier layer on the first region and the first BBM layer on the second region; and

forming a low resistance metal layer on the second WFM layer to form a metal gate.

3. The method of claim 2 , further comprising forming the second WFM layer on a top surface and a sidewall of the diffusion barrier layer.

4. The method of claim 2 , wherein the first WFM layer comprises a p-type WFM layer and the second WFM layer comprises a n-type WFM layer.

5. The method of claim 1 , wherein the first BBM layer and the diffusion barrier layer comprise a same material.

6. The method of claim 1 , further comprising forming a second BBM layer on the substrate before forming the first BBM layer.

7. The method of claim 6 , wherein the first BBM layer and the second BBM layer comprise different materials.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: UNITED MICROELECTRONICS CORP.
To: STELLAR SEMICONDUCTOR JAPAN GK
Reel/Frame 071913/0125 →
Priority Claims (1)
TW 107134933 · Oct 3, 2018 · national
Continuity (4)
Division 17709385 · Mar 30, 2022
Continuation 16907287 · Jun 21, 2020
Division 16177368 · Oct 31, 2018
Related Publication 20230369441A1 · Nov 16, 2023
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