Fabrication of a vertical fin field effect transistor with reduced dimensional variations
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
1. A method of forming fin pattern regions on a substrate of an integrated circuit, the method comprising:
forming a first fin pattern region, wherein a first integrated circuit component formed on the substrate comprises the first fin pattern region;
forming an adjacent second fin pattern region, wherein a second integrated circuit component formed on the substrate comprises the second fin pattern region;
forming a dummy fin in a pattern region gap between the first and second fin pattern regions, wherein
the first fin pattern region comprises an active fin comprising a first semiconductor material; and
the dummy fin comprises a second semiconductor material different from the first semiconductor material; and
removing the dummy fin.
2. The method of claim 1 , wherein the second fin pattern region is different from the first fin pattern region.
3. The method of claim 1 , wherein the first integrated circuit component is different from the second integrated circuit component.
4. The method of claim 1 , wherein:
the second fin pattern region is different from the first fin pattern region; and
the first integrated circuit component is different from the second integrated circuit component.
5. The method of claim 1 , wherein the pattern region gap extends along an entire side of the first or second integrated circuit component.
6. The method of claim 1 , wherein the first fin pattern region comprises a plurality of active fins, the method further comprising:
forming a dielectric fill region:
on the substrate; and
around the plurality of active fins of the first fin pattern region, wherein:
a thickness of the dielectric fill region in a direction orthogonal to an upper surface of the substrate is greater in a first region formed by removing the dummy fin than in a second region between two of the plurality of active fins.
7. The method of claim 1 , wherein the first semiconductor material is silicon.
8. The method of claim 1 , wherein the second semiconductor material is silicon germanium.
9. The method of claim 1 , wherein the second fin pattern region comprises another active fin comprising the first semiconductor material.
10. The method of claim 1 , further comprising:
forming a plurality of dummy fins in the pattern region gap; and
removing more than one dummy fin comprising the second semiconductor material from the pattern region gap.
11. The method of claim 1 , wherein:
the first integrated circuit component is a static random access memory, SRAM; and
the second integrated circuit component is a processor.
12. The method of claim 1 , wherein:
the first integrated circuit component is a static random access memory, SRAM; and
the second integrated circuit component is a graphic processor.
13. The method of claim 1 , wherein:
the first integrated circuit component is a processor; and
the second integrated circuit component is an input-output controller.
14. The method of claim 1 , wherein:
the first integrated circuit component is a graphic processor; and
the second integrated circuit component is an input-output controller.
15. The method of claim 1 , wherein:
the first integrated circuit component is a processor; and
the second integrated circuit component is a heat and/or processing control circuit.
16. The method of claim 1 , wherein:
the first integrated circuit component is a graphic processor; and
the second integrated circuit component is a heat and/or processing control circuit.
17. The method of claim 1 , wherein:
the first integrated circuit component is a processor; and
the second integrated circuit component is a register.
18. The method of claim 1 , wherein:
the first integrated circuit component is a processor; and
the second integrated circuit component is a memory.
19. The method of claim 1 , wherein:
the first integrated circuit component is a graphic processor; and
the second integrated circuit component is a register.
20. The method of claim 1 , wherein:
the first integrated circuit component is a graphic processor; and
the second integrated circuit component is a memory.
21. The method of claim 1 , wherein the active fin does not comprise silicon germanium.
22. The method of claim 21 , wherein the dummy fin comprises silicon germanium.