Package substrate including memory bridge die
View Patent ↗A package structure may include a substrate, a plurality of dies on the substrate, and a memory bridge die including a first input/output structure connected to a first semiconductor die of the plurality of dies, and a second input/output structure connected to a second semiconductor die of the plurality of dies. The first semiconductor die may be connected to the second semiconductor die through the memory bridge die.
1 . A package structure, comprising:
a substrate comprising a package substrate upper dielectric layer;
a plurality of dies on the substrate; and
a memory bridge die embedded in the package substrate upper dielectric layer and including a first input/output structure connected to a first semiconductor die of the plurality of dies, and a second input/output structure connected to a second semiconductor die of the plurality of dies, wherein the first semiconductor die is connected to the second semiconductor die through the memory bridge die,
wherein:
the substrate comprises a package substrate upper surface layer contacting a top surface of the package substrate upper dielectric layer and contacting sidewalls of the first input/output structure and sidewalls of the second input/output structure;
an interface between the first input/output structure and the memory bridge die is located within a horizontal plane including an interface between the package substrate upper dielectric layer and the package substrate upper surface layer;
the substrate comprises a core that underlies the package substrate upper dielectric layer, through vias that vertically extends through the core, and first metal interconnect structures embedded in the package substrate upper dielectric layer;
a first subset of the through vias contacts first through silicon vias in the memory bridge die;
a second subset of the through vias contacts a subset of the first metal interconnect structures; and
a sidewall of the package substrate upper dielectric layer and a sidewall of the core are located within a same vertical plane.
2 . The package structure of claim 1 , wherein the substrate comprises a package substrate and the memory bridge die is located in the package substrate.
3 . The package structure of claim 2 , wherein the first semiconductor die and the second semiconductor die are mounted on an upper surface of the memory bridge die and on an upper surface of the package substrate.
4 . The package structure of claim 3 , further comprising:
a ball grid array (BGA) on a lower surface of the package substrate opposite the upper surface of the package substrate,
wherein the memory bridge die comprises a first through silicon via (TSV), and
the package substrate comprises an additional TSV connecting the first TSV to the BGA.
5 . The package structure of claim 3 , wherein the memory bridge die extends longitudinally in a first direction, the first semiconductor die and the second semiconductor die are connected to opposite sides of the memory bridge die in a second direction perpendicular to the first direction.
6 . The package structure of claim 5 , wherein the memory bridge die comprises a first memory circuit section extending longitudinally in the first direction and connected to the first semiconductor die, and a second memory circuit section extending longitudinally in the first direction and connected to the second semiconductor die.
7 . The package structure of claim 6 , wherein the first memory circuit section and the second memory circuit section comprise at least one of a memory controller, a memory interface and a physical layer (PHY) circuit.
8 . The package structure of claim 7 , wherein the memory bridge die further comprises:
a memory array section between the first memory circuit section and the second memory circuit section, and extending longitudinally in the first direction; and
a data line connecting the first memory circuit section to the second memory circuit section, and the memory array section comprises a plurality of memory arrays connected to the data line.
9 . The package structure of claim 5 , wherein the plurality of dies further comprises:
a third semiconductor die embedded in the package substrate on a first side of the memory bridge die, wherein the first semiconductor die is mounted on the third semiconductor die; and
a fourth semiconductor die embedded in the package substrate on a second side of the memory bridge die opposite the first side of the memory bridge die in the second direction, wherein the second semiconductor die is mounted on the fourth semiconductor die.
10 . The package structure of claim 1 , wherein:
the substrate comprises a core composed of epoxy resin or a woven glass laminate;
the substrate further comprises through vias vertically extending through the core; and
the memory bridge die comprises bottom bonding pads contacting top surfaces of a subset of the through vias.
11 . The package structure of claim 1 , wherein the plurality of dies further comprises:
a third semiconductor die embedded in the package substrate upper dielectric layer on a first side of the memory bridge die and connected to the first semiconductor die; and
a fourth semiconductor die embedded in the package substrate upper dielectric layer on a second side of the memory bridge die and connected to the second semiconductor die,
wherein the package substrate upper surface layer contacts a top surface of the third semiconductor die and contacts a top surface of the fourth semiconductor die.
12 . The package structure of claim 1 , further comprising:
a first package underfill layer located between the package substrate upper surface layer and the first semiconductor die;
a second package underfill layer located between the package substrate upper surface layer and the second semiconductor die; and
a molding material layer laterally surrounding the first semiconductor die, the second semiconductor die, the first package underfill layer, and the second package underfill layer and contacting a top surface of the package substrate upper surface layer.
13 . The package structure of claim 1 , wherein:
the memory bridge die comprises a bulk semiconductor region and an active region; and
the first input/output structure contacts the active region.
14 . The package structure of claim 1 , wherein:
the substrate further comprises a package substrate lower dielectric layer underlying the core;
the substrate further comprises package substrate lower metal interconnect structures embedded in the package substrate lower dielectric layer;
the substrate further comprises a package substrate lower surface layer contacting a bottom surface of the package substrate lower dielectric layer;
the substrate further comprises a ball grid array on an opposing side of the package substrate lower surface layer as the package substrate lower dielectric layer;
a sidewall of the package substrate lower dielectric layer is located within the same vertical plane as the sidewall of the package substrate upper dielectric layer and the sidewall of the core;
the package substrate upper dielectric layer comprises a polymer material;
the package substrate upper dielectric layer comprises a material selected from the group consisting of polyimide (PI), benzocyclobutene (BCB), and polybenzobisoxazole (PBO);
the package substrate upper dielectric layer includes a plurality of layers;
the package substrate upper dielectric layer includes a build-up film;
the package substrate upper dielectric layer includes one or more package substrate upper bonding pads on a chip-side surface of the package substrate upper dielectric layer;
the package substrate upper dielectric layer includes one or more metal interconnect structures;
each of the one or more metal interconnect structures in the package substrate upper dielectric layer includes a line portion horizontally extending along the package substrate upper dielectric layer and a via portion vertically extending through the package substrate upper dielectric layer; and
the one or more metal interconnect structures in the package substrate upper dielectric layer include a metallic material selected from the group consisting of copper, tungsten, aluminum, and alloys thereof.
15 . A package structure, comprising:
a package substrate comprising a package substrate upper dielectric layer including an opening therein;
a memory die located in the opening and comprising bottom bonding pads contacting conductive structures in the package substrate, a first input/output structure located on an opposite side of the bottom bonding pads, and a second input/output structure laterally spaced from the first input/output structure;
a first semiconductor die bonded to the first input/output structure of the memory die; and
a second semiconductor die bonded to the second input/output structure of the memory die, wherein the first semiconductor die is connected to the second semiconductor die through the memory die,
wherein:
the substrate comprises a package substrate upper surface layer contacting a top surface of the package substrate upper dielectric layer and contacting sidewalls of the first input/output structure and sidewalls of the second input/output structure;
an interface between the first input/output structure and the memory die is located within a horizontal plane including an interface between the package substrate upper dielectric layer and the package substrate upper surface layer;
the substrate comprises a core that underlies the package substrate upper dielectric layer, through vias that vertically extends through the core, and first metal interconnect structures embedded in the package substrate upper dielectric layer;
a first subset of the through vias contacts first through silicon vias in the memory bridge die;
a second subset of the through vias contacts a subset of the first metal interconnect structures; and
a sidewall of the package substrate upper dielectric layer and a sidewall of the core are located within a same vertical plane.
16 . The package structure of claim 15 , further comprising:
a third semiconductor die embedded within the packaging substrate and bonded to the first semiconductor die through an additional array of microbumps; and
a fourth semiconductor die embedded within the packaging substrate and bonded to the second semiconductor die through a yet additional array of microbumps.
17 . The package structure of claim 15 , further comprising:
a first underfill material portion laterally surrounding the first semiconductor die and contacting a first segment of a top surface of the packaging substrate;
a second underfill material portion laterally surrounding the second semiconductor die and contacting a second segment of the top surface of the packaging substrate; and
a molding material layer laterally surrounding the first underfill material portion and the second underfill material portion and contacting a third segment of the top surface of the packaging substrate.
18 . A package structure, comprising:
a package substrate comprising a package substrate upper dielectric layer that includes an opening therein;
a memory die located in the opening and comprising a first input/output structure and a second input/output structure;
a first semiconductor die comprising first microbumps that are bonded to the first input/output structure of the memory die through first solder balls; and
a second semiconductor die comprising second microbumps that are bonded to the second input/output structure of the memory die through second solder balls,
wherein:
the substrate comprises a package substrate upper surface layer contacting a top surface of the package substrate upper dielectric layer and contacting sidewalls of the first input/output structure and sidewalls of the second input/output structure;
an interface between the first input/output structure and the memory die is located within a horizontal plane including an interface between the package substrate upper dielectric layer and the package substrate upper surface layer;
the substrate comprises a core that underlies the package substrate upper dielectric layer, through vias that vertically extends through the core, and first metal interconnect structures embedded in the package substrate upper dielectric layer;
a first subset of the through vias contacts first through silicon vias in the memory bridge die;
a second subset of the through vias contacts a subset of the first metal interconnect structures; and
a sidewall of the package substrate upper dielectric layer and a sidewall of the core are located within a same vertical plane.
19 . The package structure of claim 18 , wherein:
a first underfill material portion laterally surrounds the first microbumps and contacts a first segment of a top surface of the package substrate upper surface layer; and
a second underfill material portion laterally surrounds the second microbumps and contacts a second segment of the top surface of the package substrate upper surface layer.
20 . The package structure of claim 18 , further comprising a package lid attached to a top surface of the packaging substrate via an adhesive and attached to top surfaces of the first semiconductor die and the second semiconductor die via a thermal interface material layer.