Clock synchronization monitoring system
In one embodiment, a system including a reference processing device includes a reference hardware clock to maintain a reference clock value, and reference clock synchronization circuitry to discipline the reference hardware clock responsively to a remote clock, which is remote to the system, and a follower processing device including a follower hardware clock to maintain a follower clock value, and follower clock synchronization circuitry to synchronize the follower hardware clock to the reference hardware clock, and provide an indication about the follower clock value to the reference processing device, wherein the reference clock synchronization circuitry is configured to monitor a quality of the synchronization of the follower hardware clock to the reference hardware clock.
1 . A system, comprising:
a follower processing device including:
a follower hardware clock to maintain a follower clock value; and
follower clock synchronization circuitry to: synchronize the follower hardware clock to a remote hardware clock; and provide an indication about the follower hardware clock to a reference processing device; and
the reference processing device including:
a reference hardware clock to maintain a reference clock value; and
reference clock synchronization circuitry, wherein:
the follower clock synchronization circuitry includes a pulse output unit to output periodic pulses indicative of the follower clock value to the reference processing device; and
the reference clock synchronization circuitry is to receive one of the periodic pulses from the pulse input unit and sample the reference clock value responsively to receiving the one periodic pulse to monitor a quality of synchronization of the follower hardware clock.
2 . The system according to claim 1 , wherein the reference clock synchronization circuitry is configured to monitor the quality of the synchronization of the follower hardware clock responsively to the provided indication about the follower hardware clock.
3 . The system according to claim 1 , wherein the follower hardware clock is not synchronized to the reference hardware clock.
4 . The system according to claim 1 , wherein the indication is a value of a clock parameter of the follower hardware clock, the clock parameter including one or more of the following: a clock time of the follower hardware clock; a clock frequency of the follower hardware clock; a stability of the follower hardware clock, a filtered noise metric of the follower hardware clock; and/or an unfiltered noise metric of the follower hardware clock.
5 . The system according to claim 1 , wherein the reference clock synchronization circuitry is configured to discipline the reference hardware clock responsively to a remote clock.
6 . The system according to claim 1 , wherein the follower clock synchronization circuitry is configured to synchronize the follower hardware clock to the reference hardware clock using a given clock synchronization method, and the reference clock synchronization circuitry is configured to monitor the quality of the synchronization of the follower hardware clock independently of the given clock synchronization method.
7 . The system according to claim 1 , further comprising data communication bus connecting the reference processing device and the follower processing device.
8 . The system according to claim 7 , wherein the reference clock synchronization circuitry and the follower clock synchronization circuitry are configured to exchange clock synchronization messages in order to synchronize the follower hardware clock to the reference hardware clock.
9 . The system according to claim 1 , further comprising a connector, wherein:
the reference processing device includes a pulse input unit;
the connector is configured to connect the pulse output unit to the pulse input unit; and
the pulse output unit is configured to output the periodic pulses indicative of the follower clock value to the pulse input unit via the connector, responsively to the follower clock value being equal to given clock values.
10 . The system according to claim 9 , wherein the reference clock synchronization circuitry is configured to send the sampled reference clock value to the follower processing device or to a management node.
11 . The system according to claim 10 , wherein the follower processing device or the management node comprises a processor to:
determine if a clock drift of the follower clock value from the reference clock value exceeds a limit responsively to the sampled reference clock value; and
perform an action responsively to the clock drift exceeding the limit.
12 . The system according to claim 9 , wherein the reference clock synchronization circuitry is configured to:
determine if a clock drift of the follower clock value from the reference clock value exceeds a limit responsively to the sampled reference clock value; and
send a request to the follower processing device or to a management node to perform an action responsively to the clock drift exceeding the limit.
13 . The system according to claim 9 , wherein the reference clock synchronization circuitry is configured to:
determine if a clock drift of the follower clock value from the reference clock value exceeds a limit responsively to the sampled reference clock value; and
perform an action responsively to the clock drift exceeding the limit.
14 . The system according to claim 13 , wherein the reference processing device includes packet processing circuitry, which is configured to block a flow of packets from the follower processing device responsively to the clock drift exceeding the limit.
15 . The system according to claim 9 , wherein the follower clock synchronization circuitry is configured to provide time-of-day (TOD) messages to the reference clock synchronization circuitry, which is configured to determine if a clock drift of the follower clock value from the reference clock value exceeds a limit responsively to the sampled reference clock value and at least one of the time-of-day messages.
16 . The system according to claim 15 , wherein the follower clock synchronization circuitry is configured to provide the time-of-day messages at a frequency greater than two times a frequency of the periodic pulses.
17 . The system according to claim 15 , wherein the follower clock synchronization circuitry is configured to provide the time-of-day messages periodically.
18 . The system according to claim 1 , wherein the reference clock synchronization circuitry is configured to receive the indication from the follower processing device and sample the reference clock value responsively to receiving the indication.
19 . The system according to claim 18 , wherein the reference clock synchronization circuitry is configured to send the sampled reference clock value to the follower processing device or to a management node.
20 . The system according to claim 19 , wherein the follower processing device or the management node comprises a processor to:
determine if a clock drift of the follower clock value from the reference clock value exceeds a limit responsively to the sampled reference clock value; and
perform an action responsively to the clock drift exceeding the limit.
21 . The system according to claim 18 , wherein the reference clock synchronization circuitry is configured to:
determine if a clock drift of the follower clock value from the reference clock value exceeds a limit responsively to the sampled reference clock value; and
send a request to the follower processing device or to a management node to perform an action responsively to the clock drift exceeding the limit.
22 . The system according to claim 18 , wherein the reference clock synchronization circuitry is configured to:
determine if a clock drift of the follower clock value from the reference clock value exceeds a limit responsively to the sampled reference clock value; and
perform an action responsively to the clock drift exceeding the limit.
23 . The system according to claim 1 , wherein the follower processing device comprises a central processing unit (CPU) or a graphics processing unit (GPU).
24 . The system according to claim 1 , wherein the follower processing device and the reference processing device are comprised in a network switch comprising packet processing circuitry and a central processing unit (CPU).
25 . The system according to claim 1 , wherein the reference processing device includes any one or more of the following: a network device to be connected to a network and connect to the remote clock over the network; a network interface controller to be connected to the network and connect to the remote clock over the network; a network switch to connect to the remote clock over the network; and a timecard to be connected to a satellite time source, which is the remote clock.
26 . A system, comprising:
a peripheral device including:
a reference hardware clock to maintain a reference clock value; and
reference clock synchronization circuitry; and
multiple host devices, each host device including:
a follower hardware clock to maintain a follower clock value; and
follower clock synchronization circuitry to: synchronize the follower hardware clock of a respective one of the host devices to a remote hardware clock; and provide an indication about the follower clock value of the respective host device to the reference processing device, wherein:
the follower clock synchronization circuitry of each host device includes a pulse output unit to output periodic pulses indicative of the follower clock value of the respective host device to the peripheral device; and
the reference clock synchronization circuitry is to receive one of the periodic pulses from the pulse input unit of each host device and sample the reference clock value responsively to receiving the one periodic pulse of each host device to monitor a quality of synchronization of the follower hardware clock of each host device responsively to the one periodic pulse of each host device.
27 . The system according to claim 26 , further comprising connectors, wherein:
the peripheral device includes a pulse input unit;
a respective one of the connectors is configured to connect the pulse output unit of each host device to the pulse input unit; and
the pulse output unit of each host device is configured to output the periodic pulses indicative of the follower clock value of the respective host device to the pulse input unit via the respective connector, responsively to the follower clock value of the respective host device being equal to given clock values.
28 . The system according to claim 27 , wherein the pulse output unit of each host device is configured to time the output of the periodic pulses in a round-robin manner with respect to other ones of the host devices.
29 . The system according to claim 27 , further comprising a pulse input-output switch to receive the periodic pulses output by the pulse output unit of each host device and output the received periodic pulses to the pulse input unit.
30 . The system according to claim 29 , wherein the pulse-input-output switch is configured to select from the periodic pulses output by the hosts devices in a round-robin manner for output to the pulse input unit.
31 . The system according to claim 29 , wherein the pulse-input-output switch is: disposed on a mother board of the host devices; or disposed on a mother board of the peripheral device; or a standalone device disposed between the host devices and the peripheral device.
32 . The system according to claim 26 , further comprising connectors, wherein:
the peripheral device includes multiple pulse input units;
a respective one of the connectors is configured to connect the pulse output unit of each host device to a respective one of the pulse input units; and
the pulse output unit of each host device is configured to output the periodic pulses indicative of the follower clock value of the respective host device to the respective pulse input unit via the respective connector, responsively to the follower clock value of the respective host device being equal to given clock values.
33 . A method, comprising:
maintaining a reference clock value;
maintaining a follower clock value;
synchronizing a follower hardware clock to a remote hardware clock;
providing an indication about the follower hardware clock to a reference processing device; and
monitoring a quality of synchronization of the follower hardware clock;
outputting periodic pulses indicative of the follower clock value to the reference processing device;
receiving one of the periodic pulses by the reference processing device; and
sampling the reference clock value responsively to receiving the one periodic pulse to monitor a quality of synchronization of the follower hardware clock.