IP Library › Granted Patent US 12,431,460
Granted Patent B2
US 12,431,460 · App. 18/352,550 · Granted Sep 30, 2025

Die processing

Inventor: Cyprian Emeka Uzoh (San Jose, CA)
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
H01L24/80H01L21/67046H01L21/67051H01L21/67132H01L21/67253H01L21/6836H01L21/6838H01L21/78H01L23/48H01L24/97H01L25/065H01L25/50H01L21/67144H01L24/81H01L2221/68322H01L2221/68336H01L2221/68363H01L2221/68381H01L2224/80006H01L2224/80011H01L2224/80012H01L2224/80013H01L2224/80019H01L2224/80031H01L2224/80895H01L2224/80896H01L2224/81005H01L2224/81801H01L2224/97
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Quick Facts
Patent No.
US 12,431,460
App. No.
18/352,550
Granted
Sep 30, 2025
Kind
B2
Abstract

Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.

Claims (49)

1. A method of forming a microelectronic assembly, the method comprising:

attaching a wafer to a carrier, wherein the wafer comprises first and second bonding surfaces and wherein attaching the wafer to the carrier comprises attaching the second bonding surface to the carrier;

singulating the wafer into a plurality of die components, wherein the plurality of die components comprises a known good die and wherein the known good die comprises a portion of the first bonding surface and a portion of the second bonding surface;

while the plurality of die components are attached to the carrier, cleaning the plurality of die components;

removing the known good die from the carrier;

directly bonding the portion of the first bonding surface to a surface of a substrate; and

cleaning the portion of the second bonding surface while the known good die is directly bonded to the substrate.

2. The method of claim 1 , further comprising:

before singulating the wafer into the plurality of die components, forming a protective layer on the first bonding surface.

3. The method of claim 2 , further comprising:

before directly bonding the portion of the first bonding surface to the surface of the substrate, cleaning the protective layer from the portion of the first bonding surface.

4. The method of claim 1 , wherein the carrier comprises dicing tape.

5. The method of claim 1 , wherein, after removing the known good die from the carrier, the portion of the second bonding surface comprises residue and wherein cleaning the portion of the second bonding surface comprises cleaning the residue from the portion of the second bonding surface.

6. The method of claim 5 , wherein the residue comprises one or more of organic residue or a portion of the carrier.

7. The method of claim 1 , wherein cleaning the portion of the second bonding surface comprises cleaning the portion of the second bonding surface with one or more of a CMP process, a brush cleaning process, or a megasonic cleaning process.

8. The method of claim 1 , wherein the known good die comprises a first known good die, the method further comprising:

after cleaning the portion of the second bonding surface while the first known good die is directly bonded to the substrate, directly bonding a second known good die to the portion of the second bonding surface of the first known good die.

9. The method of claim 8 , further comprising:

before directly bonding the second known good die to the portion of the second bonding surface of the first known good die, activating the portion of the second bonding surface of the first known good die.

10. The method of claim 8 , further comprising:

before directly bonding the second known good die to the portion of the second bonding surface of the first known good die, thermally treating the first known good die and the substrate.

11. A method of forming a microelectronic assembly, the method comprising:

attaching a wafer to a carrier, wherein the wafer comprises first and second bonding surfaces and wherein attaching the wafer to the carrier comprises attaching the second bonding surface to the carrier;

singulating the wafer into a plurality of die components, wherein the plurality of die components comprises a known good die and wherein the known good die comprises a portion of the first bonding surface and a portion of the second bonding surface;

cleaning the plurality of die components on the carrier;

after cleaning the plurality of die components, removing the known good die from the carrier;

directly bonding the portion of the first bonding surface of the known good die to a surface of a substrate;

cleaning the portion of the second bonding surface of the known good die; and

directly bonding a second die to the portion of the second bonding surface.

12. The method of claim 11 , wherein the known good die comprises a first known good die and wherein the second die comprises a second known good die.

13. The method of claim 11 , wherein cleaning the portion of the second bonding surface of the known good die comprises cleaning residue or organic residue from the portion of the second bonding surface of the known good die.

14. The method of claim 11 , wherein cleaning the portion of the second bonding surface comprises cleaning the portion of the second bonding surface with a CMP process, a brush cleaning process, or a megasonic cleaning process.

15. The method of claim 11 , further comprising:

before directly bonding the second die to the portion of the second bonding surface, activating the portion of the second bonding surface.

16. The method of claim 11 , wherein the second die comprises a third bonding surface and wherein directly bonding a second die to the portion of the second bonding surface comprises directly bonding the third bonding surface to the portion of the second bonding surface, the method further comprising:

before directly bonding the third bonding surface to the portion of the second bonding surface, activating the third bonding surface.

17. The method of claim 11 , further comprising:

after directly bonding the second die to the portion of the second bonding surface, thermally treating the known good die, the second die, and the substrate.

18. A method of forming a microelectronic assembly, the method comprising:

attaching a wafer to a carrier, wherein the wafer comprises first and second bonding surfaces and wherein attaching the wafer to the carrier comprises attaching the second bonding surface to the carrier;

applying a protective layer to the first bonding surface;

singulating the wafer into a plurality of die components, wherein the plurality of die components comprises a known good die, wherein the known good die comprises a portion of the first bonding and portion of the second bonding surface, and wherein the portion of the first bonding surface comprises a portion of the protective layer;

cleaning the known good die, wherein cleaning the known good die comprises removing the portion of the protective layer from the portion of the first bonding surface;

removing the known good die from the carrier;

directly bonding the portion of the first bonding surface to a surface of a substrate; and

after directly bonding the portion of the first bonding surface to the surface of the substrate, cleaning the portion of the second bonding surface of the known good die.

19. The method of claim 18 , wherein cleaning the portion of the second bonding surface comprises cleaning the portion of the second bonding surface with one or more of a CMP process, a brush cleaning process, or a megasonic cleaning process.

20. The method of claim 18 , wherein the known good die comprises a first known good die, the method further comprising:

after cleaning the portion of the second bonding surface while the first known good die is directly bonded to the substrate, directly bonding a second known good die to the portion of the second bonding surface of the first known good die.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2023
From: UZOH, CYPRIAN EMEKA
To: INVENSAS BONDING TECHNOLOGIES, INC.
Reel/Frame 064260/0620 →
CHANGE OF NAME Recorded Jul 14, 2023
From: INVENSAS BONDING TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 064276/0245 →
Continuity (8)
Continuation 17231965 · Apr 15, 2021
Continuation 16910432 · Jun 24, 2020
Continuation 16515588 · Jul 18, 2019
Continuation 16282024 · Feb 21, 2019
Continuation 15936075 · Mar 26, 2018
Provisional Application 62563847 · Sep 27, 2017
Provisional Application 62488340 · Apr 21, 2017
Related Publication 20240021572A1 · Jan 18, 2024
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