Mixed poly pitch design solution for power trim
An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.
1. A method comprising:
deploying a layout, wherein the layout comprises a unit including a plurality of gates;
defining a plurality of cell types based on the unit;
optimizing the layout by:
selecting one of the cell types with a pitch size combination and a gate length combination which optimizes at least one of a speed and a power of the layout; and
manufacturing a circuit with the optimized layout.
2. The method of claim 1 , further comprising optimizing the unit until the at least one of the speed and the power reaches a predetermined value.
3. The method of claim 1 , further comprising optimizing the unit a predetermined number of iterations.
4. The method of claim 1 , wherein the unit comprises:
a plurality of first gates having a first pitch size; and
a plurality of second gates having a second pitch size, wherein a number of the first gates is less than or equal to a number of the second gates and the first pitch size is less than the second pitch size.
5. The method of claim 1 , wherein the second gates have substantially the same gate length as the first gates.
6. The method of claim 1 , wherein the first and second gates have different gate lengths.
7. The method of claim 1 , wherein the number of the first gates is equal to the number of the second gates, the first gates has a first gate length, and the second gates has a second gate length greater than the first gate length.
8. The method of claim 1 , wherein the number of first gates is less than the number of the second gates, the first gates has a first gate length, and the second gates has a second gate length greater than the first gate length.
9. The method of claim 1 , wherein the first gates has a first gate length, one of the second gates has the first gate length, and one of the second gates has a second gate length greater than the first gate length.
10. The method of claim 1 , further comprising a plurality of third gates having the first pitch size, wherein the second gates are between the first and third gates.
11. The method of claim 10 , wherein a number of the third gates is equal to the number of the first gates.
12. The method of claim 10 , wherein the third gates has substantially the same gate length as the first gates.
13. The method of claim 10 , wherein the third gate has a smaller gate length than the second gates.
14. A method comprising:
defining a plurality of cell types based on a layout, wherein the layout comprises a plurality of first gates having a first pitch size and a plurality of second gates having a second pitch size greater than the first pitch size; and
optimizing the layout by:
selecting one of the cell types with a pitch size combination and a gate length combination which optimizes at least one of a speed and a power of the layout.
15. The method of claim 14 , wherein one of the first gates has a first gate length, and one of the second gates has a second gate length greater than the first gate length.
16. The method of claim 15 , wherein one of the second gates has the first gate length.
17. The method of claim 15 , wherein the layout further include a plurality of third gates having the first gate length, wherein the second gates are between the first and third gates.
18. The method of claim 17 , wherein a number of the third gates is equal to a number of the first gates.
19. The method of claim 17 , wherein the third gates has substantially the same gate length as the first gate.
20. A method comprising:
defining a plurality of cell types based on a layout, wherein the layout comprises a plurality of first gates and a plurality of second gates, one of the first gates has a first gate length, and one of the second gates has a second gate length greater than the first gate length; and
optimizing the layout by:
selecting one of the cell types with a pitch size combination and a gate length combination which optimizes at least one of a speed and a power of the layout.