Semiconductor device and manufacturing method of semiconductor device
A semiconductor device includes a first region in which a drift, base, and accumulation regions are stacked. Transistor cells are each provided partially in the first region and include at least one trench extending into the drift region. A second region includes a well region provided on an edge termination region side surrounding the first region. A third region of a predetermined width is between the first and second regions, inside of which the transistor cells are partially provided. A bottom region is provided in the first region, adjacent to a bottom of the trench, and between the accumulation and drift regions, the bottom region not extending into the third region, its upper surface located below the base region's lower surface; and first and second electrodes configured to flow current therebetween. The bottom region is spaced apart from the base region by the accumulation region in the depth direction.
1. A semiconductor device having a first principal surface and a second principal surface, the semiconductor device comprising:
a first region including a drift region of a first conductivity type, a base region of a second conductivity type, and an accumulation region of the first conductivity type;
a plurality of transistor cells in which predetermined unit structures are regularly arranged, each of the plurality of transistor cells (i) being provided at least partially in the first region and (ii) including at least one trench that extends into the drift region along a depth direction between the first principal surface and the second principal surface in which the drift region, the accumulation region, and the base region are stacked;
a second region including a well region of the second conductivity type, the well region being provided on a side of an edge termination region that surrounds the first region;
a third region provided between the first region and the second region, the third region having a predetermined width in a direction from the first region to the second region, and the plurality of transistor cells being provided at least partially inside the third region;
a bottom region of the second conductivity type that (i) is provided in the first region and adjacent to a bottom portion of the at least one trench included in at least a part of the plurality of transistor cells, (ii) is provided between the accumulation region and the drift region in the depth direction, and (iii) does not extend into the third region, an upper surface of the bottom region being located below a lower surface of the base region in the depth direction; and
a first electrode and a second electrode configured to flow current therebetween along the depth direction, wherein
in the depth direction, the bottom region is spaced apart from the base region by at least a part of the accumulation region.
2. The semiconductor device according to claim 1 , wherein
the bottom region covers a bottom portion of an adjacent trench.
3. The semiconductor device according to claim 1 , wherein
the plurality of transistor cells include:
at least one gate trench portion having a gate conductive portion;
at least one dummy trench portion having a dummy conductive portion;
at least one first mesa portion provided adjacent to the at least one gate trench portion; and
at least one second mesa portion provided adjacent to the at least one dummy trench portion,
a channel is formed in the base region included in the at least one first mesa portion when a predetermined gate voltage is applied to the gate conductive portion, and
no channel is formed in the base region included in the at least one second mesa portion even when the predetermined gate voltage is applied to the gate conductive portion.
4. The semiconductor device according to claim 3 , wherein
in the at least one first mesa portion, a boundary is formed between the upper surface of the bottom region and a lower surface of the accumulation region.
5. The semiconductor device according to claim 3 , wherein
in the at least one second mesa portion, a boundary is formed between the upper surface of the bottom region and a lower surface of the accumulation region.
6. The semiconductor device according to claim 3 , wherein
in the at least one first mesa portion, the accumulation region contacts with the lower surface of the base region and contacts with the upper surface of the bottom region.
7. The semiconductor device according to claim 3 , wherein
the accumulation region has a doping concentration 10 times or more of a doping concentration of the drift region.
8. The semiconductor device according to claim 1 , wherein
a portion in which the drift region contacts with the lower surface of the base region is provided.
9. The semiconductor device according to claim 1 , wherein
the bottom region is in an electrically floating state.
10. The semiconductor device according to claim 1 , wherein
the bottom region is located above a bottom portion of an adjacent trench.
11. The semiconductor device according to claim 1 , wherein
a peak value of a doping concentration of the bottom region is lower than a peak value of a doping concentration of the base region.
12. The semiconductor device according to claim 3 , wherein
the bottom region is not provided in the at least one second mesa portion.
13. The semiconductor device according to claim 12 , further comprising:
a plurality of diode cells that include at least one trench extending into the drift region along the depth direction, wherein
the plurality of diode cells include the at least one second mesa portion.
14. The semiconductor device according to claim 1 , wherein
the accumulation region includes a plurality of peaks in a doping concentration distribution in the depth direction.
15. The semiconductor device according to claim 1 , wherein
a depth position of a lower end of the bottom region in the depth direction is the same in the plurality of transistor cells at least partially provided in the first region.
16. The semiconductor device according to claim 1 , wherein
a thickness of the bottom region in the depth direction is partially different in the plurality of transistor cells at least partially provided in the first region.
17. The semiconductor device according to claim 1 , wherein
the at least one trench has a sidewall of a tapered shape, a width of the sidewall becoming smaller from a lower side toward an upper side in the depth direction.
18. A semiconductor device having a first principal surface and a second principal surface, the semiconductor device comprising:
a first region including a drift region of a first conductivity type, a base region of a second conductivity type, and an accumulation region of the first conductivity type;
a plurality of transistor cells in which predetermined unit structures are regularly arranged, each of the plurality of transistor cells (i) being provided at least partially in the first region and (ii) including at least one trench that extends into the drift region along a depth direction between the first principal surface and the second principal surface in which the drift region, the accumulation region, and the base region are stacked;
a second region including a well region of the second conductivity type, the well region being provided on a side of an edge termination region that surrounds the first region;
a third region provided between the first region and the second region, the third region having a predetermined width in a direction from the first region to the second region, and the plurality of transistor cells being provided at least partially inside the third region;
a bottom region of the second conductivity type that (i) is provided in the first region and adjacent to a bottom portion of the at least one trench included in at least a part of the plurality of transistor cells, (ii) is provided between the accumulation region and the drift region in the depth direction, (iii) does not extend into the third region, and (iv) forms an upper pn-junction with the accumulation region, an upper surface of the bottom region being located below a lower surface of the base region in the depth direction; and
a first electrode and a second electrode configured to flow current therebetween along the depth direction, wherein
in the depth direction, the bottom region is spaced apart from the base region by at least a part of the accumulation region.
19. A semiconductor device including an edge termination region surrounding an active region, the semiconductor device comprising:
a semiconductor substrate including a drift region of a first conductivity type;
an emitter region of the first conductivity type provided above the drift region in the semiconductor substrate and having a doping concentration higher than the drift region;
a base region of a second conductivity type provided above the drift region in the semiconductor substrate;
an accumulation region of the first conductivity type provided below the base region in the semiconductor substrate and having a doping concentration higher than the drift region;
a plurality of trench portions provided extending from a front surface of the semiconductor substrate toward a side of a rear surface of the semiconductor substrate, conductive portions being provided inside the plurality of trench portions; and
a bottom region of the second conductivity type provided between the accumulation region and the drift region in a depth direction of the semiconductor substrate such that the bottom region being provided adjacent to bottom portions of the plurality of trench portions, wherein
a well region of the second conductivity type is provided on a side of the edge termination region, the well region provided deeper than the plurality of trench portions, and
an end of the bottom region is spaced apart from the well region.