Semiconductor device
This semiconductor device includes a plurality of sets of gate trenches, a plurality of gate electrodes, a plurality of field plate electrodes, a gate wiring, and a source wiring. The plurality of field plate electrodes each include two terminals connected to the source wiring. An outer peripheral gate wiring part of the gate wiring includes a gate finger that extends along a first direction in a plan view, and an inner gate wiring part includes a gate finger that extends along a second direction in a plan view. A first set of gate trenches extend along the first direction in a plan view and cross the gate finger, and a second set of gate trenches extend in the second direction in a plan view and cross the gate finger.
1 . A semiconductor device, comprising:
a semiconductor substrate;
a semiconductor layer formed on the semiconductor substrate and including a peripheral region and an active region surrounded by the peripheral region in plan view;
sets of gate trenches formed in the semiconductor layer, the plural sets of gate trenches including a first set and a second set;
gate electrodes, each embedded in a corresponding one of the gate trenches in the plural sets of gate trenches;
field plate electrodes, each embedded in a corresponding one of the gate trenches of the plural sets of gate trenches in a state insulated from the gate electrode;
an insulation layer formed on the semiconductor layer;
a gate interconnection formed on the insulation layer and connected to the gate electrodes, the gate interconnection including a peripheral gate interconnection portion, located in the peripheral region in plan view, and an inner gate interconnection portion, located in the active region in plan view; and
a source interconnection formed on the insulation layer and separated from the gate interconnection, wherein:
each of the field plate electrodes includes two ends connected to the source interconnection;
each of the two ends is connected to the source interconnection via a field plate contact provided at the respective end;
the peripheral gate interconnection portion includes a first gate finger extending in a first direction in plan view, and the inner gate interconnection portion includes a second gate finger extending in a second direction orthogonal to the first direction in plan view;
each gate trench of the first set extends in the first direction in plan view and intersects the second gate finger; and
each gate trench of the second set extends in the second direction in plan view and intersects the first gate finger.
2 . The semiconductor device according to claim 1 , wherein:
each gate trench of the first set intersects the second gate finger between the two ends of the field plate electrode embedded in the gate trench in plan view; and
each gate trench of the second set intersects the first gate finger between the two ends of the field plate electrode embedded in the gate trench in plan view.
3 . The semiconductor device according to claim 1 , wherein the source interconnection includes:
a peripheral source interconnection portion located in the peripheral region; and
an inner source interconnection portion located in the active region.
4 . The semiconductor device according to claim 3 , wherein:
each gate trench of the first set is entirely located inside the active region;
each gate trench of the second set extends across the active region and the peripheral region;
the two ends of the field plate electrode embedded in each gate trench of the first set are both connected to the inner source interconnection portion; and
one of the two ends of the field plate electrode embedded in each gate trench of the second set is connected to the inner source interconnection portion, and the other one of the two ends is connected to the peripheral source interconnection portion.
5 . The semiconductor device according to claim 1 , wherein:
the gate electrode embedded in each gate trench of the first set is electrically connected to the second gate finger in a region where the gate trench of the first set intersects the second gate finger in plan view; and
the gate electrode embedded in each gate trench of the second set is electrically connected to the first gate finger in a region where the gate trench of the second set intersects the first gate finger in plan view.
6 . The semiconductor device according to claim 1 , wherein the second gate finger intersects two or more sets of gate trenches including the gate trenches of the first set.
7 . The semiconductor device according to claim 1 , wherein the inner gate interconnection portion further includes at least one other gate finger intersecting the second gate finger in plan view.
8 . The semiconductor device according to claim 7 , wherein the at least one other gate finger includes a gate finger extending in the first direction in plan view.
9 . The semiconductor device according to claim 7 , wherein the at least one other gate finger includes two gate fingers extending in the first direction in plan view.
10 . The semiconductor device according to claim 1 , wherein the inner gate interconnection portion further includes a third gate finger forming a T-shaped junction with the second gate finger in plan view.
11 . The semiconductor device according to claim 1 , wherein the peripheral gate interconnection portion further includes a fourth gate finger extending in the second direction in plan view.
12 . The semiconductor device according to claim 1 , wherein the plural sets of gate trenches each include gate trenches arranged parallel to one another at equal intervals.
13 . The semiconductor device according to claim 1 , further comprising:
a pair of first linking trenches extending in the second direction in plan view and linking the gate trenches of the first set to each other; and
a pair of second linking trenches extending in the first direction in plan view and linking the gate trenches of the second set to each other, wherein:
each first linking trench is formed in the semiconductor layer and has a sidewall and a bottom wall, and links the gate trenches of the first set to each other through the sidewall of the first linking trench;
each second linking trench is formed in the semiconductor layer and has a sidewall and a bottom wall, and links the gate trenches of the second set to each other through the sidewall of the second linking trench; and
the field plate electrodes embedded in the gate trenches of the first set are connected to each other in the pair of first linking trenches; the field plate electrodes embedded in the gate trenches of the second set are connected to each other in the pair of second linking trenches; and
the two ends of each of the field plate electrodes are connected to another field plate electrode.
14 . The semiconductor device according to claim 1 , wherein:
the semiconductor substrate includes a surface on which the semiconductor layer is formed, the surface including a first side extending in the first direction and a second side extending in the second direction;
each gate trench of the first set has a length of ½ or less of a dimension of the first side; and
each gate trench of the second set has a length of ½ or less of a dimension of the second side.
15 . The semiconductor device according to claim 14 , wherein each gate trench of the first set has a length of ⅓ or less of the dimension of the first side.