Buffer chip, and semiconductor package including buffer chip and memory chips

1. A buffer chip comprising:

a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller;

a chip ID reception circuit for receiving chip ID information transmitted from the memory controller;

a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information; and

a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips;

a command address reception circuit for receiving command address signals transmitted from the memory controller;

a command address delay circuit that delays, by a set latency, the command address signals received by the command address reception circuit;

a command address transmission circuit for transmitting the command address signals delayed by the command address delay circuit to the plurality of memory chips; and

a setting change circuit for changing a command address latency of the plurality of memory chips to be different from a setting value of the memory controller.

2. The buffer chip of claim 1 , wherein the number of the memory chip select signals is larger than the number of the system chip select signals.

3. The buffer chip of claim 2 , wherein the number of the memory chip select signals is equal to the number of memory chips in the plurality of memory chips.

4. The buffer chip of claim 1 , wherein a transmission timing of the memory chip select signals to the plurality of memory chips is different from a transmission timing of the delayed command address signals to the plurality of memory chips.

5. A semiconductor package comprising:

a package substrate including a plurality of terminals for communication with a memory controller and a plurality of bonding pads for communication within the package;

a buffer chip disposed on the package substrate and directly connected to the plurality of terminals of the package substrate for communication with the memory controller;

a plurality of memory chips stacked on the buffer chip; and

a plurality of wires for wire bonding, connecting the plurality of bonding pads and the plurality of memory chips,

wherein the buffer chip communicates with the memory controller through the plurality of terminals of the package substrate,

wherein the plurality of memory chips communicate with the buffer chip via wire bonding through the plurality of wires and the plurality of bonding pads of the package substrate, and

wherein the buffer chip comprises:

a chip select signal reception circuit for receiving one or more system chip select signals transmitted from the memory controller;

a chip ID reception circuit for receiving chip ID information transmitted from the memory controller;

a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information;

a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips;

a command address reception circuit for receiving command address signals transmitted from the memory controller;

a command address delay circuit that delays the command address signals, which are received by the command address reception circuit, by a set latency:

a command address transmission circuit for transmitting the command address signals delayed by the command address delay circuit to the plurality of memory chips; and

a setting change circuit for changing a command address latency of the plurality of memory chips to be different from a setting value of the memory controller.

6. The semiconductor package of claim 5 , wherein the number of the memory chip select signals is larger than the number of the system chip select signals.

7. The semiconductor package of claim 6 , wherein the number of the memory chip select signals is equal to the number of memory chips in the plurality of memory chips.

8. The semiconductor package of claim 5 , wherein a transmission timing of the memory chip select signals from the buffer chip to the plurality of memory chips is different from a transmission timing of the delayed command address signals from the buffer chip to the plurality of memory chips.

9. A buffer chip comprising:

a chip select signal reception circuit for receiving chip select signals transmitted from a memory controller;

a command address reception circuit for receiving command address signals transmitted from the memory controller;

a command address delay circuit that delays, by a set latency, the command address signals received by the command address reception circuit;

a chip select signal transmission circuit that transmits the chip select signals to a plurality of memory chips;

a command address transmission circuit for transmitting the command address signals delayed by the command address delay circuit to the plurality of memory chips; and

a setting change circuit for changing a command address latency of the plurality of memory chips to be different from a setting value of the memory controller.

10. The buffer chip of claim 9 , wherein a transmission timing of the memory chip select signals to the plurality of memory chips is different from a transmission timing of the delayed command address signals to the plurality of memory chips.