Semiconductor device and manufacturing method thereof
A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.
1 . A semiconductor device comprising:
a first redistribution layer having a first height, the first redistribution layer comprising a first dielectric and a first conductive layer;
a semiconductor die coupled to and electrically coupled to an upper side of the first redistribution layer, wherein:
the semiconductor die comprises an interconnect comprising a bonding pad, a copper pillar, and/or a bump on a lower die side of the semiconductor die and over the upper side of the first redistribution layer,
the interconnect electrically connects the semiconductor die to the first conductive layer of the first redistribution layer, and
the first height of the first redistribution layer is less than a second height of the semiconductor die;
a wire-bond wire on the first redistribution layer, wherein:
a lower end of the wire-bond wire is electrically coupled to the first conductive layer of the first redistribution layer and extends directly vertically from the first conductive layer,
an upper end of the wire-bond wire extends at least as high as an upper die side of the semiconductor die, and
a third height of the wire-bond wire is greater than the second height of the semiconductor die;
a first encapsulant that encapsulates the upper side of the first redistribution layer, the wire-bond wire, and the semiconductor die, where the first encapsulant comprises an upper encapsulant side facing away from the first redistribution layer and a lower encapsulant side facing toward the first redistribution layer;
a substrate over the upper encapsulant side of the first encapsulant, where the substrate is electrically coupled to the first conductive layer of the first redistribution layer through the wire-bond wire; and
a dielectric material having a bottom dielectric side and a top dielectric side, wherein:
a first portion of the bottom dielectric side contacts an upper die side of the semiconductor die,
a second portion of the bottom dielectric side contacts the first encapsulant, and
the top dielectric side is free of the first encapsulant.
2 . The semiconductor device of claim 1 , wherein the first encapsulant underfills directly vertically between the semiconductor die and the first redistribution layer.
3 . The semiconductor device of claim 1 , comprising:
a plurality of conductive balls coupled to a lower side of the first redistribution layer; and
a second encapsulant directly contacting the plurality of conductive balls and the first redistribution layer.
4 . The semiconductor device of claim 1 , comprising a second encapsulant contacting the substrate.
5 . The semiconductor device of claim 1 , comprising a second encapsulant contacting the first redistribution layer, wherein lateral sides of the first redistribution layer are free of the second encapsulant.
6 . The semiconductor device of claim 1 , wherein at least one lateral side of the second encapsulant is coplanar with at least one of the lateral sides of the first redistribution layer.
7 . The semiconductor device of claim 1 , wherein the lower end of the wire-bond wire is vertically lower than the lower die side.
8 . The semiconductor device of claim 1 , comprising an underfill directly vertically between the semiconductor die and the first redistribution layer and laterally surrounding the interconnect.
9 . The semiconductor device of claim 1 , wherein an uppermost end surface of the wire-bond wire is coplanar with the upper encapsulant side.
10 . A semiconductor device comprising:
a first redistribution layer having a first height, the first redistribution layer comprising a first dielectric and a first conductive layer;
a semiconductor die coupled to and electrically coupled to an upper side of the first redistribution layer, wherein:
the semiconductor die comprises an interconnect comprising a bonding pad, a copper pillar, and/or a bump on a lower die side of the semiconductor die and over the upper side of the first redistribution layer,
the interconnect electrically connects the semiconductor die to the first conductive layer of the first redistribution layer, and
the first height of the first redistribution layer is less than a second height of the semiconductor die;
a wire-bond wire on the first redistribution layer, wherein:
a lower end of the wire-bond wire is electrically coupled to the first conductive layer of the first redistribution layer and extends directly vertically from the first conductive layer,
an upper end of the wire-bond wire extends at least as high as an upper die side of the semiconductor die, and
a third height of the wire-bond wire is greater than the second height of the semiconductor die;
a first encapsulant that encapsulates the upper side of the first redistribution layer, the wire-bond wire, and the semiconductor die, where the first encapsulant comprises an upper encapsulant side facing away from the first redistribution layer and a lower encapsulant side facing toward the first redistribution layer, and wherein a fourth height of the first encapsulant is greater than the second height of the semiconductor die;
a substrate over the upper encapsulant side of the first encapsulant, where the substrate is electrically coupled to the first conductive layer of the first redistribution layer through the wire-bond wire;
a second encapsulant contacting the first redistribution layer, wherein lateral sides of the first redistribution layer are free of the second encapsulant; and
a dielectric material having a bottom dielectric side and a top dielectric side, wherein:
the bottom dielectric side contacts an upper die side of the semiconductor die, and
the top dielectric side is free of the first encapsulant.
11 . The semiconductor device of claim 10 , wherein a lateral side of the first encapsulant is coplanar with a lateral side of the substrate.
12 . The semiconductor device of claim 10 , comprising:
a plurality of conductive balls coupled to a lower side of the first redistribution layer; and
the second encapsulant directly contacting the plurality of conductive balls.
13 . The semiconductor device of claim 10 , comprising a third encapsulant contacting the substrate.
14 . The semiconductor device of claim 10 , comprising an underfill directly vertically between the semiconductor die and the first redistribution layer and laterally surrounding the interconnect.
15 . The semiconductor device of claim 10 , wherein at least one lateral side of the second encapsulant is coplanar with at least one of the lateral sides of the first redistribution layer.
16 . The semiconductor device of claim 10 , wherein the lower end of the wire-bond wire is vertically lower than the lower die side.
17 . A method of manufacturing a semiconductor device, the method comprising:
providing a first redistribution layer having a first height, the first redistribution layer comprising a first dielectric and a first conductive layer;
coupling and electrically connecting a semiconductor die to an upper side of the first redistribution layer, wherein:
the semiconductor die comprises an interconnect comprising a bonding pad, a copper pillar, and/or a bump on a lower die side of the semiconductor die and over the upper side of the first redistribution layer,
the interconnect electrically connects the semiconductor die to the first conductive layer of the first redistribution layer, and
the first height of the first redistribution layer is less than a second height of the semiconductor die;
providing a wire-bond wire on the first redistribution layer, wherein:
a lower end of the wire-bond wire is electrically coupled to the first conductive layer of the first redistribution layer and extends directly vertically from the first conductive layer,
an upper end of the wire-bond wire extends at least as high as an upper die side of the semiconductor die, and
a third height of the wire-bond wire is greater than the second height of the semiconductor die;
providing a first encapsulant that encapsulates the upper side of the first redistribution layer, the wire-bond wire, and the semiconductor die, where the first encapsulant comprises an upper encapsulant side facing away from the first redistribution layer and a lower encapsulant side facing toward the first redistribution layer;
providing a substrate over the upper encapsulant side of the first encapsulant, where the substrate is electrically coupled to the first conductive layer of the first redistribution layer through the wire-bond wire; and
providing a dielectric material having a bottom dielectric side and a top dielectric side, wherein:
a first portion of the bottom dielectric side contacts an upper die side of the semiconductor die,
a second portion of the bottom dielectric side contacts the first encapsulant, and
the top dielectric side is free of the first encapsulant.
18 . The method of claim 17 , wherein the lower end of the wire-bond wire is vertically lower than the lower die side.
19 . The method of claim 17 , comprising providing a second encapsulant contacting the first redistribution layer, wherein lateral sides of the first redistribution layer are free of the second encapsulant.
20 . The method of claim 17 , comprising providing a second encapsulant contacting the substrate.