Arithmetic logic unit (ALU) in a base die of a processing-in-memory component with cross-ALU data communication capability
A system includes memory hardware including a memory and a processing-in-memory (PIM) component. A system includes a host including at least one core. The PIM component includes a memory die (e.g., a dynamic random access memory (DRAM) die) and a base die, e.g., a logic die. The base die includes one or more PIM arithmetic logic units (ALU) and one or more sense amplifiers. In at least some implementations the base die includes a shared static random-access memory (SRAM) cache that is shared between different ALU that reside in the base die.
1 . A system comprising:
a host including at least one core; and
a processing-in-memory component communicatively coupled to the host, the processing-in-memory component comprising:
a memory; and
a base die operatively coupled to the memory, the base die comprising:
one or more arithmetic logic units; and
a static random-access memory cache configured to be directly accessed by the one or more arithmetic logic units, wherein the one or more arithmetic logic units and the static random-access memory cache are positioned within the base die of the processing-in-memory component, wherein the base die further comprises a multiplexer configured to route a first type of data operation to the one or more arithmetic logic units and a second type of data operation to the static random-access memory cache.
2 . The system of claim 1 , wherein the memory comprises a dynamic random-access memory die.
3 . The system of claim 1 , wherein the base die comprises a logic die of the processing-in-memory component.
4 . The system of claim 1 , wherein the base die further comprises one or more sense amplifiers communicatively coupled to the one or more arithmetic logic units.
5 . The system of claim 1 , wherein the base die further comprises multiple arithmetic logic units and wherein the multiple arithmetic logic units are configured to share the static random-access memory cache.
6 . The system of claim 5 , wherein the multiple arithmetic logic units are configured to share the static random-access memory cache to access data from a remote memory bank.
7 . The system of claim 1 , wherein the base die further comprises one or more sense amplifiers communicatively coupled to the one or more arithmetic logic units.
8 . A processing-in-memory component comprising:
a memory die comprising multiple memory banks; and
a base die communicatively coupled to the memory die and comprising:
one or more arithmetic logic units;
a static random-access memory cache; and
a multiplexer configured to route a first type of data operation to the one or more arithmetic logic units and a second type of data operation to the static random-access memory cache.
9 . The processing-in-memory component of claim 8 , wherein the memory die comprises a dynamic random-access memory die.
10 . The processing-in-memory component of claim 8 , wherein the base die comprises a logic die of the processing-in-memory component.
11 . The processing-in-memory component of claim 8 , wherein the base die further comprises one or more sense amplifiers communicatively coupled to the one or more arithmetic logic units.
12 . The processing-in-memory component of claim 8 , wherein the base die further comprises multiple arithmetic logic units, and wherein the multiple arithmetic logic units are configured to share the static random-access memory cache.
13 . The processing-in-memory component of claim 12 , wherein the multiple arithmetic logic units are configured to share the static random-access memory cache to access data from a remote memory bank.
14 . The processing-in-memory component of claim 8 , wherein the base die further comprises one or more sense amplifiers communicatively coupled to the one or more arithmetic logic units.
15 . A method comprising:
prefetching remote data from a remote memory bank into a static random-access memory cache located in a base die of a processing-in-memory component; and
initiating, using at least some of the remote data, a sequence of processing-in-memory operations via one or more arithmetic logic units located in the base die of the processing-in-memory component, wherein the base die further comprises a multiplexer configured to route a first type of data operation to the one or more arithmetic logic units and a second type of data operation to the static random-access memory cache.
16 . The method of claim 15 , further comprising locking a cache line of the static random-access memory cache prior to initiating the sequence of processing-in-memory operations.
17 . The method of claim 16 , further comprising explicitly releasing the locked cache line after initiating the sequence of processing-in-memory operations.
18 . The method of claim 15 , wherein the prefetching the remote data from the remote memory bank into the static random-access memory cache is based at least in part on one or more prefetch indicators accompanying at least one of a read command or a write command to the processing-in-memory component.
19 . The method of claim 15 , wherein the base die further comprises one or more sense amplifiers communicatively coupled to the one or more arithmetic logic units.
20 . The method of claim 15 , wherein the base die comprises a logic die of the processing-in-memory component.