Three-dimensional dynamic random access memory with stacked semiconductor structures
Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.
1 . A memory device, comprising:
a plurality of vertically aligned semiconductor structures extending laterally;
a plurality of independent gate structures, each gate structure coupled to a corresponding one of the semiconductor structures;
a plurality of vertically aligned capacitors, each capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the gate structures and each capacitor comprising a wraparound structure comprising an inner capacitor plate surrounding and in contact with a portion of the corresponding one of the semiconductor structures, a capacitor dielectric surrounding and in contact with the inner capacitor plate, and an outer capacitor plate surrounding and in contact with the capacitor dielectric;
a bit line contact extending vertically across a depth of the semiconductor structures, the bit line contact coupled to each of the semiconductor structures; and
a shared capacitor contact extending vertically across a depth of the capacitors and in contact with the outer capacitor plates.
2 . The memory device of claim 1 , wherein the gate structures are laterally between the capacitors and the bit line contact, the memory device further comprising:
a plurality of second independent gate structures, each second gate structure coupled to a corresponding one of the semiconductor structures; and
a plurality of second vertically aligned capacitors, each second capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the second gate structures, wherein the bit line contact is shared to provide access to the capacitors and the second capacitors.
3 . The memory device of claim 2 , further comprising:
a plurality of third vertically aligned capacitors, each third capacitor immediately laterally adjacent a corresponding one of the second capacitors.
4 . The memory device of claim 3 , wherein an outer capacitor plate of each of the second and third capacitors are in contact with a shared capacitor contact.
5 . The memory device of claim 1 , wherein the bit line contact comprises a source or drain material epitaxial to the semiconductor structures.
6 . The memory device of claim 1 , wherein the semiconductor structures comprise a plurality of nanoribbons, a plurality of nanosheets, or a plurality of fins.
7 . The memory device of claim 1 , wherein a first of the semiconductor structures has a thickness in the vertical direction of not more than 2 nm.
8 . The memory device of claim 1 , further comprising:
an integrated circuit (IC) die comprising the semiconductor structures, the gate structures, the capacitors, the bit line contact, and the capacitor contact; and
a power supply coupled to the IC die and/or a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below −25° C.
9 . A memory device, comprising:
a plurality of vertically aligned semiconductor structures extending laterally;
a bit line contact extending vertically across a depth of the semiconductor structures, the bit line contact coupled to each of the semiconductor structures;
a plurality of first gate structures, each first gate structure coupled to a corresponding one of the semiconductor structures;
a plurality of second gate structures opposite the bit line from the first gate structures such that the bit line contact is between the first gate structures and the second gate structures, each second gate structure coupled to a corresponding one of the semiconductor structures;
a plurality of first vertically aligned capacitors, each first capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the first gate structures; and
a plurality of second vertically aligned capacitors opposite the bit line from the first capacitors such that the bit line contact, the first gate structures, and the second gate structures are between the first capacitors and the second capacitors, each second capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the second gate structures.
10 . The memory device of claim 9 , further comprising:
a plurality of third vertically aligned capacitors, each third capacitor immediately laterally adjacent a corresponding one of the second capacitors.
11 . The memory device of claim 10 , wherein an outer capacitor plate of each of the second and third capacitors are in contact with a shared capacitor contact.
12 . The memory device of claim 9 , wherein each of the first capacitors comprises a wraparound structure comprising an inner capacitor plate surrounding and in contact with a portion of the corresponding one of the semiconductor structures, a capacitor dielectric surrounding and in contact with the inner capacitor plate, and an outer capacitor plate surrounding and in contact with the capacitor dielectric.
13 . The memory device of claim 9 , wherein the bit line contact comprises a material epitaxial to each of the semiconductor structures, the material extending vertically across the depth of the semiconductor structures.
14 . The memory device of claim 9 , further comprising:
an integrated circuit (IC) die comprising the semiconductor structures, the bit line contact, the first gate structures, the second gate structures, the first capacitors, and the second capacitors; and
a power supply coupled to the IC die and/or a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below −25° C.
15 . A memory device, comprising:
a plurality of vertically aligned semiconductor structures extending laterally;
a plurality of independent gate structures, each gate structure coupled to a corresponding one of the semiconductor structures;
a plurality of vertically aligned capacitors, each capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the gate structures; and
a bit line contact extending vertically across a depth of the semiconductor structures, the bit line contact coupled to each of the semiconductor structures and the bit line contact comprising a material epitaxial to each of the semiconductor structures, the material extending vertically across the depth of the semiconductor structures.
16 . The memory device of claim 15 , wherein the gate structures are laterally between the capacitors and the bit line contact, the memory device further comprising:
a plurality of second independent gate structures, each second gate structure coupled to a corresponding one of the semiconductor structures; and
a plurality of second vertically aligned capacitors, each second capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the second gate structures, wherein the bit line contact is shared to provide access to the capacitors and the second capacitors.
17 . The memory device of claim 16 , further comprising:
a plurality of third vertically aligned capacitors, each third capacitor immediately laterally adjacent a corresponding one of the second capacitors.
18 . The memory device of claim 17 , wherein an outer capacitor plate of each of the second and third capacitors are in contact with a shared capacitor contact.
19 . The memory device of claim 15 , wherein the bit line contact comprises a source or drain material epitaxial to the semiconductor structures.
20 . The memory device of claim 15 , wherein the semiconductor structures comprise a plurality of nanoribbons, a plurality of nanosheets, or a plurality of fins.
21 . The memory device of claim 15 , wherein a first of the semiconductor structures has a thickness in the vertical direction of not more than 2 nm.
22 . The memory device of claim 15 , further comprising:
an integrated circuit (IC) die comprising the semiconductor structures, the gate structures, the capacitors, and the bit line contact; and
a power supply coupled to the IC die and/or a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below −25° C.