Chip design method using secondary development capability of EDA software
The present application discloses a chip design method using secondary development capability of EDA software. On the basis of a chip having design and verification of a main function being completed, the feature steps comprise: customizing and adding, on an EDA software development platform, parameters required for an operating environment corresponding to the chip, automatically adding a schematic diagram of at least one of an environmental stabilization system used for implementing temperature compensation and an environmental stabilization system used for implementing electromagnetic shielding, combining same with a chip schematic diagram and drawing to obtain a layout. According to the method, the optimization operation of adding an environmental stabilization system is separated from design of the main function of the chip, and on the basis that design and verification of the main function of the chip are completed and the original chip design layout is kept with few changes, the secondary development capability of EDA software is used for separately optimizing and automatically adding the environmental stabilization system to the original chip design layout; thus, the difficulty and time consumption in chip design are reduced to the greatest extent, and the chip can obtain the capability of normally implementing functions in temperatures and electromagnetic environments that are more severe than those expected in the original design.
1 . A chip design method using secondary development capability of EDA software, on the basis of a chip having design and verification of a main function thereof completed, comprising: automatically adding at least one of an environmental stabilization system used for implementing temperature compensation and an environmental stabilization system used for implementing electromagnetic shielding;
wherein, when automatically adding the environmental stabilization system used for implementing electromagnetic shielding, the method comprises:
step S 21 , preconfiguring at least one function module corresponding to electromagnetic shielding in an EDA software development platform for chip design, wherein the electromagnetic shielding comprises: addition of a metal layer, shielding by grounding;
step S 22 , selecting to add electromagnetic shielding on a chip design development platform, and inputting at least one environment parameter related to electromagnetic field intensity; and
step S 23 , automatically calculating, by the EDA software development platform, a width and a thickness of a covering metal layer based on the environmental parameter related to electromagnetic field intensity as well as a frame size and coordinates of a completed chip design, calling the function module corresponding to electromagnetic shielding to be added to the completed chip design based on the calculated width and thickness of the covering metal layer, and drawing a corresponding schematic diagram and a layout.
2 . The chip design method using secondary development capability of EDA software according to claim 1 , wherein, when automatically adding the environmental stabilization system used for implementing temperature compensation, the method comprises:
step S 11 , preconfiguring at least one function module corresponding to temperature compensation in an EDA software development platform for chip design;
step S 12 , selecting to add temperature compensation on a chip design development platform, and inputting at least one temperature-related parameter which is required for an environment; and
step S 13 , automatically calculating, by the EDA software development platform, a heat generation power required for temperature compensation based on the temperature-related parameter which is required for an environment, calling, based on the calculated heat generation power, the function module corresponding to temperature compensation to be added to a completed chip design, and drawing a corresponding schematic diagram and a layout.
3 . The chip design method using secondary development capability of EDA software according to claim 2 , wherein the temperature-related parameter which is required for an environment at least comprises: a lower limit of temperature stability point, a chip operating environment temperature, a package heat dissipation speed, and an estimated chip heat generation power.
4 . The chip design method using secondary development capability of EDA software according to claim 2 , wherein the function module corresponding to temperature compensation comprises: a heating control circuit and a heating circuit based on a silicon substrate and resistors, the number, distribution and wiring size of the resistors in the heating circuit are calculated by the EDA software development platform based on a heat generation power of each resistor, and the frame size and coordinates of the completed chip design.
5 . The chip design method using secondary development capability of EDA software according to claim 4 , wherein the heating control circuit is connected between a power source section and a heating current-limiting module of the completed chip design, and comprises a second temperature detection circuit for controlling on-off of the power source section, a first temperature detection circuit for driving and controlling the heating current-limiting module, and a positive temperature coefficient resistor and a negative temperature coefficient resistor which are respectively connected with the first and second temperature detection circuits via signal communication and configured to measure the temperature of the chip, and switching thresholds of output control signals of the first and second temperature detection circuits are adjustably set by the EDA software development platform.
6 . The chip design method using secondary development capability of EDA software according to claim 2 , wherein, in the step S 12 , inputting at least one temperature-related parameter which is required for the environment comprises: removing the frame of the completed chip design, and in the step S 13 , calling the function module corresponding to temperature compensation to be added to the completed chip design and drawing the corresponding schematic diagram and the layout comprises: calculating a safe voltage difference between a peripheral heating circuit and a circuit within the frame that has been removed by the EDA software development platform.
7 . The chip design method using secondary development capability of EDA software according to claim 2 , wherein the temperature-related parameter which is required for the environment inputted in the step S 12 comprises: a maximum size limited by chip packaging, and in the step S 13 , using the maximum size limited by chip packaging as a range constraint by the EDA software development platform to add the function module corresponding to temperature compensation and draw a schematic diagram and a layout.
8 . The chip design method using secondary development capability of EDA software according to claim 1 , wherein, in the step S 23 , when electromagnetic shielding is done by addition of a metal layer, calling the function module corresponding to electromagnetic shielding to be added to the completed chip design comprises:
calculating a thickness of a required metal layer according to the environmental parameter related to electromagnetic field intensity, and in combination with the frame size and coordinates of the completed chip design, obtaining a size and coordinates of a metal layer covering an entire surface of a chip, the metal layer being a polygon; and
according to the obtained size and coordinates of the metal layer covering the entire surface of the chip, adding an grounded loop island at a bottom layer around the perimeter of the completed chip design and starting growth until the metal layer is closed at the top so that the completed chip design is completely covered by the metal layer, wherein the metal layer at the top is left with openings at locations corresponding to chip contacts, and each face of the polygonal metal layer is grounded.
9 . The chip design method using secondary development capability of EDA software according to claim 8 , wherein, according to the obtained size and coordinates of the metal layer covering the entire surface of the chip, adding the grounded loop island at the bottom layer around the perimeter of the completed chip design and starting growth until the metal layer is closed at the top so that the completed chip design is completely covered by the metal layer comprises:
performing a logical operation extending a certain width for the windows corresponding to the chip contacts and located on the metal layer at the top, so that the metal layer with the openings and covering the entire chip is obtained, wherein the positions and sizes of the openings are one-to-one corresponding to the positions and sizes of the contacts.