Device providing multiple threshold voltages and methods of making the same
A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.
1. A method, comprising:
receiving a workpiece, wherein the workpiece includes a plurality of regions having a first, a second, a third, a fourth, a fifth, and a sixth regions;
forming a dielectric layer on the plurality of regions;
forming a first patterned layer of a first dipole material on the dielectric layer in the third, the fourth, the fifth, and the sixth regions;
forming a second patterned layer of a second dipole material on the dielectric layer in the fifth and the sixth regions;
performing a first thermal drive-in operation at a first temperature;
forming a third patterned layer of a third dipole material on the dielectric layer in the second, the fourth, and the sixth regions;
performing a second thermal drive-in operation at a second temperature, wherein the second temperature is lower than the first temperature; and
forming a gate electrode layer over the dielectric layer.
2. The method of claim 1 , further comprising performing a third thermal drive-in operation after performing the second thermal drive-in operation.
3. The method of claim 1 , further comprising performing a third thermal drive-in operation between performing the first thermal drive-in operation and performing the second thermal drive-in operation.
4. The method of claim 1 , wherein performing the first thermal drive-in operation has a first time duration, and performing the second thermal drive-in operation has a second time duration greater than the first time duration.
5. The method of claim 1 , wherein the dielectric layer is a first dielectric layer, and
wherein the method further comprises:
forming a second dielectric layer over the first dielectric layer,
forming a fourth patterned layer of a fourth dipole material on the second dielectric layer in the third, the fourth, the fifth, and the sixth regions,
forming a fifth patterned layer of a fifth dipole material on the second dielectric layer in the fifth and the sixth regions,
performing a third thermal drive-in operation,
forming a sixth patterned layer of a sixth dipole material on the second dielectric layer in the second, the fourth, and the sixth regions, and
performing a fourth thermal drive-in operation.
6. The method of claim 5 , wherein forming the gate electrode layer over the first dielectric layer includes forming the gate electrode layer over the second dielectric layer.
7. The method of claim 1 , wherein the first patterned layer and the second patterned layer have different thicknesses.
8. A semiconductor structure, comprising:
a substrate;
a first transistor disposed over the substrate and including:
a first channel,
a first interfacial layer disposed over the first channel, and
a first gate dielectric layer and a first gate electrode layer disposed over the first interfacial layer; and
a second transistor disposed over the substrate and including:
a second channel,
a second interfacial layer disposed over the second channel, and
a second gate dielectric layer and a second gate electrode layer disposed over the second interfacial layer,
wherein the first gate dielectric layer includes a first dipole material composition having a first maximum concentration at an interface between the first gate dielectric layer and the first interfacial layer, and
wherein the second gate dielectric layer includes a second dipole material composition having a second maximum concentration an interface between the second gate dielectric layer and the second interfacial layer and greater than the first maximum concentration.
9. The semiconductor structure of claim 8 , further comprising a third transistor disposed over the substrate and including:
a third channel,
a third interfacial layer disposed over the third channel, and
a third gate dielectric layer and a third gate electrode layer disposed over the third interfacial layer,
wherein the third gate dielectric layer includes a third dipole material composition having a third maximum concentration at a half-thickness line of the third gate dielectric layer.
10. The semiconductor structure of claim 9 , wherein the third maximum concentration is greater than the second maximum concentration.
11. The semiconductor structure of claim 9 , wherein the third maximum concentration is greater than the first maximum concentration and smaller than the second maximum concentration.
12. The semiconductor structure of claim 8 , wherein the first channel is one of a first plurality of channels of the first transistor, and the second channel is one of a second plurality of channels of the second transistor.
13. The semiconductor structure of claim 8 , wherein the first dipole material composition includes a first dipole element, and the second dipole material composition includes the first dipole element and a second dipole element.
14. The semiconductor structure of claim 8 , wherein the first dipole material composition has a concentration greater than zero at an interface between the first channel and the first interfacial layer.
15. A semiconductor structure, comprising:
a substrate;
a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer; and
a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer,
wherein the first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer, and
wherein the second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.
16. The semiconductor structure of claim 15 , further comprising a third transistor disposed over the substrate and including a third channel, a third interfacial layer over the third channel, a third gate dielectric layer over the third interfacial layer, and a third gate electrode layer over the third gate dielectric layer,
wherein the third gate dielectric layer includes a third dipole material composition having a third maximum concentration at a half-thickness line of the third gate dielectric layer and smaller than the first maximum concentration.
17. The semiconductor structure of claim 15 , wherein the first dipole material composition includes a first dipole element and a second dipole element, and the second dipole material composition includes the first dipole element, the second dipole element, and a third dipole element.
18. The semiconductor structure of claim 15 , further comprising a third transistor disposed over the substrate and including a third channel, a third interfacial layer over the third channel, a third gate dielectric layer over the third interfacial layer, and a third gate electrode layer over the third gate dielectric layer,
wherein the third gate dielectric layer includes a third dipole material composition having a third maximum concentration at an interface between the third gate dielectric layer and the third interfacial layer.
19. The semiconductor structure of claim 18 , wherein the third maximum concentration is smaller than the first maximum concentration.
20. The semiconductor structure of claim 15 , wherein the first transistor further includes a third gate dielectric layer over the first gate dielectric layer,
wherein the first gate electrode layer is disposed over the third gate dielectric layer, and
wherein the third gate dielectric layer includes the first dipole material composition.