IP Library › Granted Patent US 6,963,188
Granted Patent B2
US 6,963,188 · App. 10/818,865 · Granted Nov 8, 2005

On-chip power supply interface with load-independent current demand

Assignee: Atmel Corporation
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Quick Facts
Patent No.
US 6,963,188
App. No.
10/818,865
Granted
Nov 8, 2005
Kind
B2
Abstract

An on-chip interface circuit located between the chip's power supply pin and its internal circuitry senses the current load of the internal circuitry and provides a supplemental current sink so that total current demand seen at the power supply pin is substantially constant despite the internal circuitry's variable load. Sensing of the internal load is done by a sensor stage with two parallel branches, each branch having a resistor, a sense transistor, and a current mirror device, which together produce a voltage drop as a control voltage output which relates the internal load to a constant reference current. The supplemental current sink is in the form of a transistor operating below saturation in its linear region and whose gate is coupled to receive the control voltage output of the sensor stage.

Claims (22)

1. An interface circuit for use between a power supply pin and internal circuitry with a variable load, the interface circuit providing a substantially load-independent current demand at the power supply pin, the interface circuit comprising:

sensing means, coupled between the power supply pin at an interface input and the internal circuitry at an interface output, for sensing a current load of the internal circuitry and producing a control voltage corresponding to said current load; and

current sinking means, responsive to said control voltage, for sinking extra current in inverse relation to said current load of the internal circuitry, such that total current demand by both the internal circuitry and the extra current sinking means is at least substantially constant up to saturation of said current sinking means.

2. The interface circuit as in claim 1 , further comprising means for establishing a constant reference current for use by said load sensing means.

3. The interface circuit as in claim 2 , wherein said reference current means and said load sensing means both have current mirror devices with the gates of the current mirror devices coupled together such that a constant current corresponding to said reference current is established through a current path in said load sensing means.

4. The interface circuit as in claim 1 , wherein said load sensing means comprises first and second branches connected in parallel between the interface input and ground, each branch having a resistor, a sense transistor and a current mirror device, the current mirror devices in the two branches establishing corresponding current flow in the branches through said mirror devices, said sense transistors in the two branches having a common gate connection between the sense transistor and mirror device of the first branch, said resistor in the first branch providing substantially larger resistance than said resistor in the second branch, the interface output being coupled between the resistor and sense transistor of the second branch such that current flow through the resistor in the second branch provides a measure of the current load of the internal circuitry in the form of a voltage drop, the voltage drop being provided as a control voltage that is output between the sense transistor and current mirror device of the second branch.

5. The interface circuit as in claim 1 , wherein the means for sinking extra current comprises a transistor connected between the interface output and ground, the transistor having a gate coupled to receive the control voltage from the load sensing means, the transistor operating below saturation in a substantially linear region of an operating characteristic of the transistor.

6. An interface circuit for use between a power supply pin and internal circuitry with a variable load, the interface circuit providing a substantially load-independent current demand at the power supply pin, the interface circuit comprising:

a reference current stage having a constant current source and a current mirror device in series establishing a constant reference current therethrough;

a load sensing stage coupled between the power supply pin at an interface input and the internal circuitry at an interface output, the load sensing stage including first and second branches connected in parallel between the interface input and ground, each branch having a resistor, a sense transistor and a current mirror device, the current mirror devices in the two branches and the current mirror device in the reference current stage having the gates of the current mirror devices coupled together to establish current flow through the mirror devices of the two branches which correspond to the constant reference current, the sense transistors of the two branches having a common gate connection between the sense transistor and current mirror device of the first branch, said resistor of the first branch providing substantially larger resistance than said resistor in the second branch, the interface output being coupled between the resistor and sense transistor of the second branch such that current flow through the resistor in the second branch provides a measure of the current load of the internal circuitry in the form of a voltage drop, the voltage drop being provided as a control voltage that is output from the load sensing stage between the sense transistor and current mirror device of the second branch; and

a supplemental load stage including a transistor connected between the interface output and ground, the transistor having a gate coupled to receive the control voltage output from the load sensing stage, the transistor operating below saturation in a substantially linear region of an operating characteristic of the transistor such that the transistor sinks extra current in inverse relation to the current load of the internal circuitry.

7. A method of providing a substantially load-independent current demand at a power supply pin of an integrated circuit notwithstanding a variable load by internal circuitry of the integrated circuit, the method comprising:

sensing, by an interface circuit provided between the power supply pin and the internal circuitry, a current load of the internal circuitry and producing a control voltage corresponding to the sensed current load; and

sinking, by a supplemental load device of the interface circuit responsive to the control voltage, extra current in inverse relation to the current load of the internal circuitry, such that total current demand by both the internal circuitry and the supplemental load device is substantially constant up to a saturation level of the supplemental load device.

8. The method of claim 7 , wherein sensing the current load and producing a corresponding control voltage involves providing a voltage drop from an interface input coupled to the power supply pin across an output impedance of the interface circuit that is coupled to the internal circuitry, the voltage drop across the output impedance being referenced against a voltage drop across a proportional resistor for a constant reference current.

9. The method of claim 8 , wherein the referencing of the voltage drop is accomplished by a load sensing stage of the interface circuit comprising first and second parallel branches connected between the interface input and ground, each branch having a resistor, a sense transistor and a current mirror device, the current mirror devices establishing corresponding current flow in the branches through said mirror devices, the sense transistors having a common gate connection between the sense transistor and mirror device of the first branch, the resistor in the first branch being the proportional resistor that has a substantially larger resistance than the resistor in the second branch, the resistor in the second branch being the output impedance with the interface output coupled between the resistor and sense transistor of the second branch, and wherein the voltage drop across the output impedance is provided as the control voltage between the sense transistor and current mirror device of the second branch.

10. The method of claim 7 , wherein the supplemental load device that sinks the extra current is a transistor connected between an interface output coupled to the internal circuitry and ground, and having a gate coupled to receive the control voltage, the transistor operating below saturation in a substantially linear region of an operating characteristic of the transistor.

11. An integrated circuit comprising:

at least one power supply pin;

internal circuitry drawing current through the power supply pin; and

an interface circuit electrically coupled between the power supply pin and the internal circuitry and providing a supplemental current load such that total current demand by both the internal circuitry and interface circuit is substantially constant at the power supply pin notwithstanding any current load variation by the internal circuitry.

12. The integrated circuit as in claim 11 , wherein the interface circuit includes means for sensing a current load of said internal circuitry and producing a control voltage corresponding thereto and means responsive to the control voltage for sinking extra current in inverse relation to the sensed current load of the internal circuitry.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2004
From: WICH, MATTHEW T.
To: ATMEL CORPORATION
Reel/Frame 015220/0117 →
Continuity (1)
Related Publication 20050218872A1 · Oct 6, 2005