Dual phase pulse modulation system
A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface is externally programmable for a particular data format. An encoder is coupled to the configurable interface and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2 M distinct data pulse widths. The system further includes a decoder coupled to the configurable interface, which is able to convert the serial input data into parallel data.
1. An electronic circuit configured to transmit data signals over a data link, comprising:
a configurable interface configured to accept data from an external source, the interface being externally programmable for a particular data format;
means for stripping any clock signal from the data from the external source; and
an encoder coupled to the configurable interface and configured to convert parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2 M distinct data pulse widths where M is an integer greater than or equal to one.
2. The system of claim 1 wherein the external source is a microcontroller.
3. The system of claim 1 wherein the external source is an imaging device.
4. The system of claim 1 wherein the configurable interface is configured to accept microprocessor data.
5. The system of claim 1 wherein the configurable interface is configured to accept image-based data.
6. The system of claim 1 wherein M has a value of two.
7. A system configured to receive data signals over a data link, comprising:
a configurable interface configured to accept serial data through a serial data input, the interface being externally programmable for a particular data format;
wherein the serial data accepted through the serial data input is originally parallel data from which is stripped any clock signals, and
a decoder coupled to an output of the interface, the decoder configured to receive a signal consisting of a series of alternately high and low signal pulses of specified widths corresponding to M-bit groups of data bite, with each of the high and low data pulses having one of 2 M distinct data pulse widths where M is an integer greater than or equal to one, the decoder further configured to convert the serial data into parallel data.
8. The system of claim 7 wherein the external source is a microcontroller.
9. The system of claim 7 wherein the external source is an imaging device.
10. The system of claim 7 wherein the configurable interface is configured to accept microprocessor data.
11. The system of claim 7 wherein the configurable interface is configured to accept image-based data.
12. The system of claim 7 wherein M has a value of two.
13. A system configured to transmit and receive data signals over a data link, comprising:
a configurable interface configured to accept parallel data from an external sources the interface being externally programmable for a particular data format;
means for stripping the parallel data of any clock signal;
an encoder coupled to the configurable interface and configured to convert parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2 M distinct data pulse widths where M is an integer greater than or equal to one; and
a decoder coupled to the configurable interface and configured to convert the serial output data into parallel data.
14. The system of claim 13 wherein the external source is a microcontroller.
15. The system of claim 13 wherein the external source is an imaging device.
16. The system of claim 13 wherein the configurable interface is configured to accept microprocessor data.
17. The system of claim 13 wherein the configurable interface is configured to accept image-based data.
18. The system of claim 13 wherein M has a value of two.
19. A method for converting parallel image data into serial image data, comprising:
receiving parallel image data:
stripping any pixel clock from the parallel image data; and
converting the parallel image data into serial data, the serial data having high and low data pulses with each of the high and low data pulses encoded to have one of 2 M distinct data pulse widths where M is an integer greater than or equal to one.
20. The method of claim 19 further comprising stripping any synchronization signal from the parallel image data.
21. The method of claim 20 further comprising concatenating two or more parallel image data words, the words having been stripped of any synchronization signals.
22. The method of claim 21 further comprising appending a single horizontal synchronization signal and a single vertical synchronization signal to the concatenated image data.
23. The method of claim 19 wherein M has a value of two.
24. A method for converting parallel microprocessor data into serial microprocessor data, comprising:
receiving parallel microprocessor data;
stripping any clock signal from the microprocessor data;
stripping any chip select data from the microprocessor data; and
converting the parallel microprocessor data into serial data, the serial data having high and low data pulses with each of the high and low data pulses encoded to have one of 2 M distinct data pulse widths where M is an integer greater than or equal to one.
25. The method of claim 24 wherein M has a value of two.
26. A method for converting parallel data signals into a serial data signal, comprising:
receiving parallel data;
stripping any clock signals from the parallel data; and
converting the parallel data into serial data, the serial data having high and low data pulses with each of the high and low data pulses encoded to have one of 2 M distinct data pulse widths.
27. The method of claim 26 wherein M has a value of two.