FinFET SRAM cell using inverted FinFET thin film transistors
View Patent ↗An integrated circuit, such as a SRAM cell ( 130 ), including an inverted FinFET transistor (P 2 ) and a FinFET transistor (N 3 ). The inverted FinFET transistor includes a first gate region ( 108 ) formed by semiconductor structure ( 100 ) on a substrate, a first body region comprised of a semiconductor layer ( 104 ), having a first channel region ( 112 ) disposed on the first gate region and a source ( 110 ) and drain ( 114 ) formed on either side of the first channel region. The FinFET transistor (N 3 ) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure ( 102 ), having a second channel region ( 118 ), and a source ( 116 ) and drain ( 120 ) formed on either side of the second channel region, and a second gate region ( 122 ) comprised of the semiconductor layer, disposed on the second channel region.
1. An integrated circuit having at least first and second inverted FinFet transistors (P 2 , N 3 ),
said at least first FinFet transistor (P 2 ), comprising:
a first gate region ( 108 ) including a semiconductor structure ( 100 ) on a substrate; and
a first body region including a semiconductor layer ( 104 ) having a first channel region ( 112 ) disposed on the first gate region and a source ( 110 ) and drain ( 114 ) formed on either side of the first channel region; and
said at least second FinFet transistor (N 3 ) coupled to said at least first transistor, comprising:
a second body region including the semiconductor structure ( 102 ) having a second channel region ( 118 ) and a source ( 116 ) and drain ( 120 ) formed on either side of the second channel region; and
a second gate region ( 122 ) including the semiconductor layer ( 104 ), disposed on the second channel region.
2. The integrated circuit of claim 1 , wherein the semiconductor structure ( 100 , 102 ) comprises a silicon fin.
3. The integrated circuit of claim 1 , wherein the drain ( 114 ) of the first transistor (P 2 ) is connected to the gate ( 122 ) of the second transistor (N 3 ) by the semiconductor layer ( 104 ).
4. The integrated circuit of claim 1 , further comprising a third FinFet transistor (N 1 ), that includes:
a third body region including the semiconductor structure ( 100 ), having a third channel region ( 126 ) and a source ( 128 ) and drain ( 124 ) formed on either side of the third channel region; and
a third gate region ( 129 ) including the semiconductor layer ( 106 ) disposed on the third channel region.
5. The integrated circuit of claim 4 , wherein the gate ( 108 ) of the first FinFet transistor (P 2 ) is connected to the drain ( 124 ) of the third FinFet transistor (N 1 ) by the semiconductor structure ( 100 ).
6. The integrated circuit of claim 4 , wherein the FinFet first transistor (P 2 ) comprises an inverted FinFET transistor.
7. The integrated circuit of claim 1 , further comprising an underpass ( 80 ), wherein the underpass allows a portion of the semiconductor structure ( 82 ) having a first doping type to insulatively pass under a portion of the semiconductor layer ( 86 ) having the first doping type.
8. The integrated circuit of claim 1 , wherein the first FinFET transistor (P 2 ) comprises a pull-up transistor of an SRAM cell ( 130 ), and the second FinFET transistor (N 3 ) comprises a pull-down transistor of the SRAM cell.