Offset cancellation and reduced source induced 1/f noise of voltage reference by using bit stream from over-sampling analog-to-digital converter
An over-sampling analog-to-digital converter (ADC) uses a chopper stabilized voltage reference with improved reference voltage offset cancellation and reduced source induced 1/f noise. The chopper stabilized voltage reference receives chopper clocks that have been correlated with the serial bitstream produced by the sigma-delta modulator of the ADC. The chopper clocks are generated so that the reference voltage produces for each distinct bitstream level an independent sequence of voltages that comprise alternatively positive and negative voltage reference offset contributions. After integration (averaging) is performed within the sigma-delta modulator, these equal and opposite reference offset contributions cancel out regardless of the bit pattern comprising the bitstream.
1. An over-sampling analog-to-digital converter (ADC) having improved voltage reference offset cancellation and reduced source induced 1/f noise, said ADC comprising:
a sigma-delta modulator having plus and minus analog inputs, plus and minus reference voltage inputs and an output supplying serial digital information therefrom, wherein the sigma-delta modulator comprises:
a plus input voltage capacitor having a capacitance of A*C/2,
a minus input voltage capacitor having a capacitance of A*C/2,
a first pair of switches adapted for switchably coupling the plus and minus input voltage capacitors to the plus and minus analog inputs, respectively,
a second pair of switches adapted for switchably coupling the plus and minus input voltage capacitors to the minus and the plus inputs, respectively,
a plus reference voltage capacitor having a capacitance of C/2, a minus reference voltage capacitor having a capacitance of C/2,
a fifth pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to plus and minus reference voltage inputs, respectively,
a sixth pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltage inputs, respectively,
a seventh switch adapted for switchably coupling the plus and minus reference voltage capacitors together,
a third plurality of switches coupled to the plus and minus input voltage capacitors and the plus and minus reference voltage capacitors, and adapted for switchably coupling a common mode voltage, VCM, to these capacitors, and
a fourth pair of switches adapted for coupling the plus and minus input voltage capacitors and the plus and minus reference voltage capacitors to a differential input of an amplifier,
wherein the switches are sequenced in a charge phase and a transfer phase to produce five equally distributed voltage outputs from the amplifier of A*VIN+VREF, A*VIN+VREF/2, A*VIN+0, A*VIN−VREF/2 and A*VIN−VREF, where A is gain, VIN is an input voltage, and VREF is a reference voltage;
a chopper stabilized voltage reference supplying plus and minus reference voltages to the plus and minus reference voltage inputs of the sigma-delta modulator; and
a chopper clock control coupled to the chopper stabilized voltage reference and the output of the sigma-delta modulator,
wherein the chopper clock control uses the serial digital information from the output of the sigma-delta modulator to generate chopper clocks that cause the chopper stabilized voltage reference to supply reference voltages to the sigma-delta modulator that comprise an equal number of positive voltage offsets and negative voltage offsets for each level of digital-to-analog conversions, and
whereby an average of the positive and negative voltage offsets cancel out voltage offset contribution to the reference voltages supplied to the sigma-delta modulator.
2. The ADC according to claim 1 , wherein the chopper stabilized voltage reference comprises:
a bandgap voltage reference;
a chopper modulator coupled to the bandgap voltage reference;
a differential amplifier coupled to an output of the chopper modulator; and
a chopper demodulator coupled to an output of the differential amplifier, wherein the chopper modulator and demodulator are controlled by the chopper clock control, and an output of the chopper demodulator supplies the reference voltage to the reference input of the sigma-delta modulator.
3. The ADC according to claim 2 , wherein the chopper stabilized voltage reference further comprises an output buffer amplifier.
4. The ADC according to claim 3 , wherein the output buffer amplifier has differential inputs and differential outputs.
5. The ADC according to claim 1 , wherein the sigma-delta modulator is a multi-level sigma-delta modulator, and the serial digital information comprises a plurality of serial bit streams from outputs of the sigma-delta modulator, wherein an equal number of reference voltages having positive voltage offsets and negative voltage offsets for each level of the digital-to-analog conversions are supplied to the multi-level sigma-delta modulator.
6. The ADC according to claim 1 , further comprising a digital filter coupled to the output of the sigma-delta modulator and adapted to convert the serial digital information into digital words representative of samples of analog voltages on the analog input of the sigma-delta modulator.
7. The ADC according to claim 6 , wherein the digital filter is a digital low pass filter.
8. The ADC according to claim 6 , wherein the digital filter is a digital decimation filter.
9. The ADC according to claim 1 , wherein the sigma-delta modulator is a two-level sigma-delta modulator, and the serial digital information comprises a single serial bit stream.
10. The ADC according to claim 9 , wherein the two-level sigma-delta modulator comprises:
an analog voltage summation circuit coupled to the analog input;
a two-level digital-to-analog converter (DAC) having an output coupled to the analog voltage summation circuit, a reference voltage input coupled to the chopper stabilized voltage reference, and a control input;
an analog voltage integrator coupled to an output of the analog voltage summation circuit; and
a voltage comparator having an analog input, a gate input and a gated output, the analog input is coupled to an output of the analog voltage integrator, wherein the gated output of the voltage comparator is at a first logic level when a first voltage is on the analog input, and is at a second logic level when a second voltage is on the analog input;
sample clocks are coupled to the gate input of the gated voltage comparator, whereby the output logic state at the gated output of the voltage comparator is held between the sample clocks;
the gated output of the voltage comparator is coupled to the control input of the two-level DAC, wherein the gated output supplies the serial digital information from the sigma-delta modulator; and
the two-level DAC supplies
a first voltage to the reference input of the analog voltage summation circuit when the control input of the two-level DAC is at the first logic level, and
a second voltage to the reference input of the analog voltage summation circuit when the control input of the two-level DAC is at the second logic level, whereby the first and second voltages from the two-level DAC are combined with respective ones of the voltages sampled at the analog input by the analog voltage summation circuit.
11. The ADC according to claim 10 , wherein the first voltage is the plus reference voltage and the second voltage is the minus reference voltage.
12. The ADC according to claim 11 , wherein the first voltage is the minus reference voltage and the second voltage is the plus reference voltage.
13. The ADC according to claim 9 , wherein the chopper clock control comprises:
two D Flip-Flops, each of the two D Flip-Flops being associated with a respective one of the two-level sigma-delta modulator,
wherein each of the two D Flip-Flops stores chopper and respective level values based upon logic levels of the bitstream; and
a synchronizing latch,
wherein the synchronizing latch synchronizes operation of the chopper clocks from the chopper clock control,
whereby the chopper clocks are output from the synchronizing latch such that the reference voltages supplied to the two-level sigma-delta modulator comprise an equal number of positive voltage offsets and negative voltage offsets for each level of the two levels of the digital-to-analog conversions, and
whereby the average of the positive and negative voltage offsets cancel out voltage offset contribution to the reference voltages supplied to the two-level sigma-delta modulator.