Maintaining input and/or output configuration and data state during and when coming out of a low power mode
A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a “low power state wake-up and restore” signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.
1. An integrated circuit device having a low power mode with a maintained configuration of an input receiver, and a maintained configuration and output data state of an output driver, comprising:
a plurality of logic circuits having a low power mode;
an input-output (I/O) node coupled to the plurality of logic circuits, the I/O node comprises an I/O keeper cell coupled to an output driver and an input receiver, wherein the output driver and the input receiver are configurable;
wherein when the I/O keeper cell receives an enter low power mode signal the I/O keeper cell maintains the input receiver according to a receive configuration and the output driver according to an output configuration and at an output data state that were determined by the plurality of logic circuits before entering the low power mode;
wherein when the I/O keeper cell receives a wake-up and restore from low power mode signal the I/O keeper cell returns control of the receive configuration of the input receiver and the output configuration and the output data state of the output driver to the plurality of logic circuits; and
a low power mode register that stores logic levels for and controls the enter low power mode signal and the wake-up and restore from low power mode signal.
2. The integrated circuit device according to claim 1 , wherein the enter low power mode signal and the wake-up and restore from low power mode signal are one signal having a first logic level and a second logic level, respectively, whereby when the one signal is at the first logic level the enter low power mode signal is asserted and when the one signal is at the second logic level the wake-up and restore from low power mode signal is asserted.
3. The integrated circuit device according to claim 2 , wherein the first logic level is a logic “1” and the second logic level is a logic “0.”
4. The integrated circuit device according to claim 2 , wherein the first logic level is a logic “0” and the second logic level is a logic “1.”
5. The integrated circuit device according to claim 1 , wherein the driver and the receiver are coupled to an external I/O connection of an integrated circuit package.
6. The integrated circuit device according to claim 1 , wherein the integrated circuit device is selected from the group consisting of microprocessor, microcontroller, digital signal processor (DSP), programmable logic array (PLA), and application specific integrated circuit (ASIC).
7. The integrated circuit device according to claim 1 , wherein the I/O node and low power mode register are powered from the same power source.
8. The integrated circuit device according to claim 1 , wherein the I/O node and low power mode register are powered from one power source and the plurality of logic circuits are powered from another power source.
9. The integrated circuit device according to claim 8 , wherein the another power source is turned off when in the low power mode.
10. An integrated circuit device having a low power mode with a maintained configuration and output data state of an output driver, comprising:
a plurality of logic circuits having a low power mode;
an output node coupled to the plurality of logic circuits, the output node comprises an output keeper cell coupled to an output driver, wherein the output driver is configurable;
wherein when the output keeper cell receives an enter low power mode signal the output keeper cell maintains the output driver at a configuration and an output data state that were determined by the plurality of logic circuits before entering the low power mode;
wherein when the output keeper cell receives a wake-up and restore from low power mode signal the output keeper cell returns control of the configuration and the output data state of the driver to the plurality of logic circuits; and
a low power mode register that stores logic levels for and controls the enter low power mode signal and the wake-up and restore from low power mode signal.
11. The integrated circuit device according to claim 10 , wherein the enter low power mode signal and the wake-up and restore from low power mode signal are one signal having a first logic level and a second logic level, respectively, whereby when the one signal is at the first logic level the enter low power mode signal is asserted and when the one signal is at the second logic level the wake-up and restore from low power mode signal is asserted.
12. The integrated circuit device according to claim 11 , wherein the first logic level is a logic “1” and the second logic level is a logic “0.”
13. The integrated circuit device according to claim 11 , wherein the first logic level is a logic “0” and the second logic level is a logic “1.”
14. The integrated circuit device according to claim 10 , wherein the driver is coupled to an external output connection of an integrated circuit package.
15. The integrated circuit device according to claim 10 , wherein the integrated circuit device is selected from the group consisting of microprocessor, microcontroller, digital signal processor (DSP), programmable logic array (PLA), and application specific integrated circuit (ASIC).
16. The integrated circuit device according to claim 10 , wherein the output node and low power mode register are powered from the same power source.
17. The integrated circuit device according to claim 10 , wherein the output node and low power mode register are powered from one power source and the plurality of logic circuits are powered from another power source.
18. The integrated circuit device according to claim 17 , wherein the another power source is turned off when in the low power mode.
19. An integrated circuit device having a low power mode and with a maintained configuration of an input receiver, comprising:
a plurality of logic circuits having a low power mode;
an input node coupled to the plurality of logic circuits, the input node comprises an input keeper cell coupled to an input receiver, wherein the input receiver is configurable;
wherein when the input keeper cell receives an enter low power mode signal the input keeper cell maintains the input receiver at a configuration that was determined by the plurality of logic circuits before entering the low power mode;
wherein when the input keeper cell receives a wake-up and restore from low power mode signal the input keeper cell returns control of the configuration of the input receiver to the plurality of logic circuits; and
a low power mode register that stores logic levels for and controls the enter low power mode signal and the wake-up and restore from low power mode signal.
20. The integrated circuit device according to claim 19 , wherein the enter low power mode signal and the wake-up and restore from low power mode signal are one signal having a first logic level and a second logic level, respectively, whereby when the one signal is at the first logic level the enter low power mode signal is asserted and when the one signal is at the second logic level the wake-up and restore from low power mode signal is asserted.
21. The integrated circuit device according to claim 20 , wherein the first logic level is a logic “1” and the second logic level is a logic “0.”
22. The integrated circuit device according to claim 20 , wherein the first logic level is a logic “0” and the second logic level is a logic “1.”
23. The integrated circuit device according to claim 19 , wherein the receiver is coupled to an external input connection of an integrated circuit package.
24. The integrated circuit device according to claim 19 , wherein the integrated circuit device is selected from the group consisting of microprocessor, microcontroller, digital signal processor (DSP), programmable logic array (PLA), and application specific integrated circuit (ASIC).
25. The integrated circuit device according to claim 19 , wherein the input node and low power mode register are powered from the same power source.
26. The integrated circuit device according to claim 19 , wherein the input node and low power mode register are powered from one power source and the plurality of logic circuits are powered from another power source.
27. The integrated circuit device according to claim 26 , wherein the another power source is turned off when in the low power mode.