Base platforms with combined ASIC and FPGA features and process of using the same
A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.
1. A base platform design for a configurable integrated circuit platform, wherein the base platform design comprises:
a memory for storing data;
a pre-diffused metal-programmable transistor fabric containing a plurality of transistors configurable to different configurations of logic and memory by the addition of at least one metallization layer to the platform, which selectively connects transistors of the transistor fabric into a configuration of at least one of the logic or memory;
firmware-configurable logic blocks, the metallization layer selectively connecting at least one of the firmware-configurable logic blocks to the metal-programmable transistor fabric to receive input signals that are connected to the logic configured in the metal-programmable transistor fabric, the at least one firmware-configurable logic block being configurable by firmware to execute functions on the input signals; and
a multiplexer coupled to the logic configured in the metal-programmable transistor fabric and the at least one firmware-configurable logic block, and an enable input selectively controlling the multiplexer to output results from either the logic configured in the metal-programmable transistor fabric or the at least one firmware-configurable logic block.
2. The base platform design according to claim 1 , wherein the design further defines hardmacs, including memory, and at least one memory containing the firmware.
3. The base platform design according to claim 1 , characterized by the absence of memory for the firmware, wherein the firmware is arranged to be resident in an off-platform configuration memory.
4. A base platform design for a configurable integrated circuit platform, wherein the base platform design comprises:
a pre-diffused metal-programmable transistor fabric containing a plurality of transistors configurable to different configurations of logic and memory by the addition of at least one metallization layer to the platform, which selectively connects transistors of the transistor fabric into a configuration of at least one of the logic or memory;
first firmware-configurable logic blocks, which are configurable by firmware to execute functions on signals;
second firmware-configurable logic blocks, the metallization layer selectively connecting the second firmware-configurable logic blocks to the metal-programmable transistor fabric to receive input signals to the logic configured in the metal-programmable transistor fabric, the second firmware-configurable logic blocks being configurable by firmware to execute functions on the input signals; and
a controller, which selectively outputs results from the logic configured in the metal-programmable transistor fabric or the second firmware-configurable logic blocks.
5. An integrated circuit comprising:
a base platform for a configurable integrated circuit platform, wherein the base platform comprises:
a pre-diffused metal-programmable transistor fabric containing a plurality of transistors configurable to different configurations of logic and memory by the addition of at least one metallization layer to the platform; and
firmware-configurable logic blocks, which are configurable by firmware to execute functions on signals within the integrated circuit; and
at least one metallization layer, which selectively connects the transistors of the metal-programmable transistor fabric into a selected configuration of at least one of the logic or memory, the metallization layer selectively connecting at least one firmware-configurable logic block to the metal-programmable transistor fabric to receive input signals connected to the logic configured in the metal-programmable transistor fabric, the at least one firmware-configurable logic block being configurable by the firmware to execute functions on the input signals; and
a multiplexer on the base platform, which is coupled to the logic configured in the metal-programmable transistor fabric and the at least one firmware-configurable logic block, and an enable input selectively controlling the multiplexer to output results from either the logic formed in the metal-programmable transistor fabric or the at least one firmware-configurable logic block.