IP Library › Granted Patent US 7,760,476
Granted Patent B2
US 7,760,476 · App. 11/759,351 · Granted Jul 20, 2010

Threshold voltage method and apparatus for ESD protection

Assignee: Atmel Corporation
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Quick Facts
Patent No.
US 7,760,476
App. No.
11/759,351
Granted
Jul 20, 2010
Kind
B2
Abstract

An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground.

Claims (19)

1. An electrostatic discharge protection circuit, comprising:

a shunt device coupled between a power supply terminal and ground, the shunt device capable of shunting current from the power supply terminal to ground in response to a trigger signal received at a shunt device input;

a latch coupled to the shunt device input, the latch capable of latching the trigger signal received at a latch input;

a buffer coupled to the latch input, the buffer capable of receiving the trigger signal at a buffer input;

a comparator coupled between the power supply terminal, ground, and the buffer input, the comparator capable of responding to an electrostatic discharge event and producing the trigger signal at a comparator output, wherein the comparator comprises:

a first current mirror comprising a first sense device coupled to the power supply terminal and a first mirror device coupled between the comparator output and the power supply terminal;

a plurality of bias devices coupled to the first sense device, at least two of the plurality of bias devices coupled in series at a bias output line;

a transconductance device comprising an input coupled to the power supply terminal and a control input coupled to the bias output line;

a second current mirror comprising a second sense device coupled between the transconductance device and ground and a second mirror device coupled between the comparator output and ground, the second mirror device coupled in series with the first mirror device; and

a compensating device coupled between the plurality of bias devices and ground.

2. The electrostatic discharge protection circuit of claim 1 , wherein the plurality of bias devices is capable of producing a bias voltage on the bias output line proportionate to a first sense current flowing through the first sense device and the plurality of bias devices, the bias voltage determining a second sense current flowing through the transconductance device.

3. The electrostatic discharge protection circuit of claim 1 , wherein the comparator is capable of producing the trigger signal at the comparator output based on a current flowing through the first mirror device and the second mirror device.

4. The electrostatic discharge protection circuit of claim 1 , wherein a resultant current through the series coupled mirror devices activates the trigger signal.

5. The electrostatic discharge protection circuit of claim 1 , wherein the first mirror device is capable of producing an incident current and the second mirror device is capable of accepting an absorption current.

6. The electrostatic discharge protection circuit of claim 1 , wherein the series coupling of mirror devices is capable of producing a resultant current equal to the greater of an incident current flowing through the first mirror device or an absorption current flowing through the second mirror device.

7. The electrostatic discharge protection circuit of claim 6 , wherein the trigger signal is activated when the absorption current is greater than the incident current.

8. The electrostatic discharge protection circuit of claim 1 , wherein a first sense current through the first sense device produces an incident current through the first mirror device and a second sense current through the second sense device produces an absorption current through the second mirror device.

9. The electrostatic discharge protection circuit of claim 1 , wherein the first mirror device is capable of producing an incident current less than an absorption current through the second mirror device with a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeding the incident current producing the trigger signal at the comparator output activating the shunt device.

10. The electrostatic discharge protection circuit of claim 1 , wherein the compensating device is capable of compensating a temperature dependent variation of a threshold voltage of the first sense device, the compensating device providing a voltage drop across the compensating device corresponding to the voltage drop across the first sense device due to temperature variation.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2007
From: RIVIERE, ANTOINE; DEMOLLI, FREDERIC; BERNARD, DAVID
To: ATMEL CORPORATION
Reel/Frame 019454/0049 →
Continuity (1)
Related Publication 20080304191A1 · Dec 11, 2008