Systems and apparatus for main memory with non-volatile type memory modules, and related technologies
A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
1. A system comprising:
a motherboard having processor sockets coupled to memory module sockets in one or more memory channels via printed circuit board traces, each of the processor sockets configured to receive a processor and each of the memory module sockets configured to receive a memory module;
one or more processors plugged into some but less than all of the processor sockets such that at least one processor socket is without a processor, each of the one or more processors including one or more processing cores; and
at least one memory controller plugged into the at least one processor socket without a processor, the at least one memory controller configured to control random read and write accesses of data to memory other than volatile memory in at least one of the one or more memory channels.
2. The system of claim 1 , further comprising:
at least one non-volatile memory module respectively plugged into at least one of the memory module sockets in the one or more memory channels.
3. The system of claim 2 , wherein
the memory module sockets are dual in-line memory module (DIMM) sockets, and
the at least one non-volatile memory module is a non-volatile dual in-line memory module.
4. The system of claim 2 , wherein
at least one memory device of the non-volatile memory module is a NOR flash electrically erasable programmable read only memory (EEPROM) integrated circuit chip.
5. The system of claim 2 , wherein
the at least one memory controller is a non-volatile memory controller.
6. The system of claim 1 , wherein
the at least one memory controller is a dual memory controller and is further configurable to control read and write accesses of data to dynamic random access memory in at least another one of the one or more memory channels.