Composition of memory cell with resistance-switching layers
A memory cell including a first electrode, a second electrode and a first resistance-switching layer located between the first and second electrodes. The first resistance-switching layer comprises hafnium silicon oxynitride.
1. A memory cell comprising:
first electrode;
a second electrode;
a first resistance-switching layer located between the first and second electrodes, wherein the first resistance-switching layer comprises hafnium silicon oxynitride; and
a steering element comprising a diode located in series with the first resistance-switching layer.
2. The memory cell of claim 1 , further comprising:
a second resistance-switching layer between the first and second electrodes; and
a conductive or semiconductor layer between the first resistance-switching layer and the second resistance-switching layer.
3. The memory cell of claim 2 , wherein:
the conductive or semiconductive intermediate layer is selected from the group consisting of TiN, Al, Zr, La, Y, Ti, TiAlN, Ti x N y , W and TiAl alloys.
4. The memory cell of claim 2 , wherein the second resistance-switching layer comprises hafnium silicon oxynitride.
5. The memory cell of claim 1 , wherein at least one of the first and second electrodes is selected from the group consisting of W, WSix, WN, TiN, TiSix, SiGe, TiAlN, NiSi, Ni, Co, CoSi, n+Si, and p+Si, n+n+SiC and p+SiC.
6. The memory cell of claim 1 , wherein the first resistance-switching layer is amorphous.
7. The memory cell of claim 1 , wherein a nitrogen content of the first resistance-switching layer is greater than 0 and less than 20 at %.
8. The memory cell of claim 7 , wherein the first resistance-switching layer comprises 15-30 at % hafnium, 10-20 at % silicon and 30-70 at % oxygen.
9. The memory cell of claim 1 , wherein the thickness of the first resistance-switching layer is 10 Å-5 nm.
10. A method of making memory cell comprising:
forming a first electrode over a substrate;
forming a first resistance-switching layer comprising hafnium silicon oxynitride over the first electrode;
forming a steering element comprising a diode located in series with the first resistance-switching layer; and
forming a second electrode over the first resistance-switching layer.
11. The method of claim 10 , further comprising:
forming a second resistance-switching layer between the first and second electrodes; and
forming a conductive or semiconductive layer between the first resistance-switching layer and the second resistance-switching layer.
12. The method of claim 11 , wherein:
the conductive or semiconductive intermediate layer is selected from the group consisting of TiN, Al, Zr, La, Y, Ti, TiAlN, Ti x N y , W and TiAl alloys.
13. The method of claim 11 , wherein the second resistance-switching layer comprises hafnium silicon oxynitride.
14. The method of claim 10 , wherein at least one of the first and second electrodes is selected from the group consisting of W, WSix, WN, TiN, TiSix, SiGe TiAlN, NiSi, Ni, Co, CoSi, n+Si and p+Si, n+n+SiC and p+SiC.
15. The method of claim 10 , wherein the first resistance-switching layer is amorphous.
16. The method of claim 10 , further comprising heating the amorphous memory cell to a temperature between 600 and 1100 C such that the first resistance-switching layer remains amorphous after the step of heating.
17. The method of claim 10 , wherein a nitrogen content of the first resistance-switching layer is greater than 0 and less than 20 at %.
18. The method of claim 17 , wherein the first resistance-switching layer comprises 15-30 at % hafnium, 10-20 at % silicon and 30-70 at % oxygen.
19. The method of claim 10 , wherein the thickness of the first resistance-switching layer is 10 Å-5 nm.
20. The method of claim 10 , wherein the step of forming the first resistance-switching layer comprises blanket depositing of hafnium silicon oxynitride film over the first electrode.
21. The method of claim 10 , wherein the step of forming the first resistance-switching layer comprises blanket depositing a hafnium silicon oxide film over the first electrode followed by nitriding the film to convert the film to the hafnium silicon oxynitride.
22. The method of claim 21 , wherein the step of nitriding is selected from plasma nitridation, thermal nitridation or nitrogen ion implantation.
23. A memory device, comprising:
a memory array comprising a plurality of memory cells, each memory cell comprising a steering element in series with a resistance-switching memory element, each resistance-switching memory element comprising an intermediate layer between first and second resistance-switching layers, the first and second resistance-switching layers comprising hafnium silicon oxynitride;
a plurality of word lines and bit lines;
each memory cell having one end in communication with a respective bit line of the plurality of bit lines, and another end in communication with a respective word line of the plurality of word lines; and
control circuitry in communication with the plurality of word lines and bit lines, the control circuitry applies a voltage to at least one of the memory cells via the respective bit line and the word line thereof, to cause the resistance-switching memory element of the at least one of the memory cells to switch from one resistance state to another resistance state.
24. The memory device of claim 23 , wherein each steering element comprises a diode.
25. The memory device of claim 23 , wherein the memory array is monolithic three-dimensional array including multiple levels of memory cells, each memory level including multiple memory cells in a cross-point array.
26. A memory cell comprising:
a first electrode;
a second electrode; and
a first resistance-switching layer located between the first and second electrodes, wherein the first resistance-switching layer comprises hafnium silicon oxynitride;
wherein a nitrogen content of the first resistance-switching layer is greater than 0 and less than 20 at %.
27. A method of making memory cell comprising:
forming a first electrode over a substrate;
forming a first resistance-switching layer comprising hafnium silicon oxynitride over the first electrode; and
forming a second electrode over the first resistance-switching layer;
wherein a nitrogen content of the first resistance-switching layer is greater than 0 and less than 20 at %.
28. A method of making memory cell comprising:
forming a first electrode over a substrate;
forming a first resistance-switching layer comprising hafnium silicon oxynitride over the first electrode;
forming a second electrode over the first resistance-switching layer; and
heating the memory cell to a temperature between 600 and 1100 C such that the first resistance-switching layer remains amorphous after the step of heating.
29. A method of making memory cell comprising:
forming a first electrode over a substrate;
forming a first resistance-switching layer comprising hafnium silicon oxynitride over the first electrode; and
forming a second electrode over the first resistance-switching layer;
wherein the step of forming the first resistance-switching layer comprises blanket depositing a hafnium silicon oxide film over the first electrode followed by nitriding the film to convert the film to the hafnium silicon oxynitride.