Nanowire FET with trapezoid gate structure
In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
1. A semiconductor structure comprising:
a nanowire comprising a channel region and extension source and drain regions on opposing sides of the channel region; and
a trapezoid gate structure present on the channel region of the nanowire, wherein the channel region has a first width on a first surface of the nanowire and a second width on an opposing second surface of the nanowire, wherein the second width is greater than the first width and the sidewall of the trapezoid gate structure is aligned to the first width on the first surface of the nanowire and the second width on the opposing second surface of the nanowire.
2. The semiconductor device of claim 1 , wherein the first surface of the nanowire is an upper surface of the nanowire, and the second surface of the nanowire is a lower surface of the nanowire.
3. The semiconductor device of claim 1 , wherein the trapezoid gate structure is present surrounding at least a portion of a circumference of the nanowire.
4. The semiconductor device of claim 1 , wherein the trapezoid gate structure is a gate all around (GAA) structure, or is an omega gate structure.
5. The semiconductor device of claim 1 , wherein the trapezoid gate structure comprises a low-k gate dielectric layer in direct contact with the channel region of the nanowire, a high-k gate dielectric layer in direct contact with the low-k gate dielectric layer, a metal nitride layer in direct contact with the low-k gate dielectric layer, and a gate conductor in direct contact with the metal nitride layer.
6. The semiconductor device of claim 5 , wherein the low-k gate dielectric has a dielectric constant of 4.0 or less, and the high-k gate dielectric has a dielectric constant of greater than 4.0.
7. The semiconductor device of claim 5 , wherein the high-k gate dielectric layer is selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof.
8. The semiconductor device of claim 5 , wherein the metal nitride layer is selected from the group consisting of WN, WSiN, TiN, TiSiN, TaN, TaSiN, TiTaN, TaRuN and combinations thereof.
9. The semiconductor device of claim 5 , wherein the low-k gate dielectric is comprised of silicon oxide, the high-k gate dielectric is comprised of HfO 2 , the metal nitride layer is comprised of TaN, and the gate conductor is comprised of polysilicon.
10. The semiconductor device of claim 1 , wherein the nanowire has a diameter of 2 nm or less.
11. The semiconductor device of claim 1 , wherein the upper surface of the trapezoid gate structure has a width ranging from 5 nm to 200 nm.
12. The semiconductor device of claim 11 , wherein the difference in width between the first width of the channel portion and the second width of the channel portion is greater than 10 nm.
13. The semiconductor device of claim 1 , wherein a base surface of the trapezoid gate structure has a width ranging from 10 nm to 250 nm.
14. The semiconductor device of claim 1 , wherein the interface angle of the sidewall of the trapezoid gate structure to the first surface of the nanowire ranges from 45° to 85°.
15. The semiconductor device of claim 1 , the first width of the channel portion ranges from 70 nm to 90 nm and the second width of the channel portion ranges from 80 nm to 100 nm.
16. The semiconductor device of claim 1 further comprising SOI pad regions adjacent to the extension source and drain regions of the nanowire.
17. The semiconductor device of claim 16 , wherein the SOI pad regions comprise deep source regions and deep drain regions.
18. The semiconductor device of claim 17 , wherein the deep source region and the deep drain regions are doped to an n-type conductivity or a p-type conductivity.
19. A semiconductor structure comprising:
a nanowire comprising a channel region and extension source and drain regions on opposing sides of the channel region; and
a trapezoid gate structure present on the channel region of the nanowire, wherein the trapezoid gate structure comprises a low-k gate dielectric layer in direct contact with the channel region of the nanowire, a high-k gate dielectric layer in direct contact with the low-k gate dielectric layer, a metal nitride layer in direct contact with the low-k gate dielectric layer, and a gate conductor in direct contact with the metal nitride layer.