finFET devices
A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.
1. A finFET structure, comprising:
a plurality of finFET structures;
a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures; and
a conductive layer on the stress material which spans across and is in contact with at least two of the plurality of finFET structures.
2. The finFET structure of claim 1 , wherein the stress material is provided on both sides of the plurality of finFET structures.
3. The finFET structure of claim 1 , wherein:
the gate stack comprises the conductive layer, the stress material, gate material, and dielectric material;
the plurality of finFET structures extend perpendicular from the gate stack; and
a space between an extended portion of the plurality of finFET structures is devoid of the stress material.
4. The finFET structure of claim 1 , wherein the stress material is a nitride material.
5. The finFET structure of claim 4 , wherein the plurality of finFET structures comprises a gate material deposited on a dielectric material, and the stress material on the gate material.
6. The finFET structure of claim 1 , wherein the stress material has a lattice constant different than that of a gate material of the plurality of finFET structures.
7. The finFET structure of claim 6 , wherein the stress material is an insulator and the gate material is one of a poly and metal material.
8. The finFET structure of claim 1 , wherein the gate stack comprises the conductive layer, the stress material, gate material, and dielectric material, in order.
9. The finFET structure of claim 8 , wherein the conductive layer is directly on a top planarized surface of the stress material.
10. The finFET structure of claim 8 , wherein the conductive layer is in contact with a top surface of the dielectric material and the gate material.
11. A finFET structure, comprising:
a plurality of finFET gate structures comprising a gate material deposited on a dielectric material;
an insulator stress material provided in a space between each of fin of the plurality of finFET gate structures and on sides of the fins; and
a conductive layer on the insulator stress material,
wherein:
the insulator stress material has a lattice constant different than that of the gate material used for the plurality of finFET gate structures; and
the insulator stress material is formed only on the gate material.
12. The finFET structure of claim 11 , wherein the plurality of finFET gate structures includes a gate stack comprising the conductive layer, the insulator stress material, the gate material, the dielectric material, in order.
13. The finFET structure of claim 11 , wherein the insulator stress material is a nitride material.
14. The finFET structure of claim 11 , wherein the gate material is one of metal material and poly material.
15. The finFET structure of claim 11 , wherein the insulator stress material is provided on both sides of the plurality of finFET gate structures.
16. The finFET structure of claim 11 , wherein the insulator stress material merges the plurality of finFET gate structures in source/drain areas.
17. The finFET structure of claim 11 , wherein the conductive layer is directly on a top planarized surface of the insulator stress material.
18. The finFET structure of claim 11 , wherein the conductive layer spans across at least two fins of the plurality of finFET gate structures.
19. The finFET structure of claim 11 , wherein the conductive layer is in contact with a top surface of the dielectric material and the gate material.