Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths
Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.
1. A semiconductor structure comprising:
a first semiconductor region;
a second semiconductor region positioned laterally adjacent to said first semiconductor region; and
a trench isolation structure laterally surrounding said first semiconductor region and said second semiconductor region such that said first semiconductor region is electrically isolated from said second semiconductor region,
said first semiconductor region having first end portions and a first center portion positioned laterally between said first end portions, said first center portion being narrower than said first end portions and having a first width, and
said second semiconductor region having second end portions and a second center portion positioned laterally between said second end portions, said second center portion being narrower than said second end portions and having a second width that is less than said first width.
2. The semiconductor structure of claim 1 , further comprising:
a first isolating cap on said first center portion and having said first width, said first isolating cap comprising a dielectric body positioned laterally between dielectric spacers; and
a second isolating cap on said second center portion and having said second width, said second isolating cap being essentially identical to said dielectric body.
3. The semiconductor structure of claim 2 , said dielectric body and said dielectric spacers comprising different dielectric materials.
4. The semiconductor structure of claim 2 , said dielectric body comprising silicon nitride and said dielectric spacers comprising any one of silicon oxide, silicon oxynitride and silicon carbide.
5. The semiconductor structure of claim 1 , further comprising, a gate structure on first sidewalls of said first center portion and on second sidewalls of said second center portion.
6. The semiconductor structure of claim 1 , said first center portion comprising a first channel region of a first multi-gate field effect transistor and said second center portion comprising a second channel region of a second multi-gate field effect transistor.
7. The semiconductor structure of claim 6 , said first multi-gate field effect transistor and said second multi-gate field effect transistor having a same conductivity type.
8. The semiconductor structure of claim 6 , said first multi-gate field effect transistor and said second multi-gate field effect transistor having different conductivity types.
9. A semiconductor structure comprising:
a first semiconductor region on an insulator layer;
a second semiconductor region on said insulator layer positioned laterally adjacent to said first semiconductor region; and
a trench isolation structure laterally surrounding said first semiconductor region and said second semiconductor region such that said first semiconductor region is electrically isolated from said second semiconductor region,
said first semiconductor region having first end portions and a first center portion positioned laterally between said first end portions, said first center portion being narrower than said first end portions and having a first width, and
said second semiconductor region having second end portions and a second center portion positioned laterally between said second end portions, said second center portion being narrower than said second end portions and comprising two parallel sections, each of said parallel sections having a second width that is less than said first width.
10. The semiconductor structure of claim 9 , further comprising:
a first isolating cap on said first center portion and having said first width, said first isolating cap comprising a dielectric body positioned laterally between dielectric spacers; and
second isolating caps on said parallel sections of said second center portion, each of said second isolating caps having said second width and being essentially identical to one of said dielectric spacers.
11. The semiconductor structure of claim 10 , said dielectric body and said dielectric spacers comprising different dielectric materials.
12. The semiconductor structure of claim 11 , said dielectric body comprising silicon nitride and said dielectric spacers comprising any one of silicon oxide, silicon oxynitride and silicon carbide.
13. The semiconductor structure of claim 9 , further comprising a gate structure on first sidewalls of said first center portion and on second sidewalls of said parallel sections of said second center portion.
14. The semiconductor structure of claim 9 , said first center portion comprising a first channel region of a first multi-gate field effect transistor and said second center portion comprising said parallel sections of said second center portion comprising a second channel region of a second multi-gate field effect transistor.
15. The semiconductor structure of claim 14 , said first multi-gate field effect transistor and said second multi-gate field effect transistor having a same conductivity type.
16. The semiconductor structure of claim 14 , said first multi-gate field effect transistor and said second multi-gate field effect transistor having different conductivity types.