Impedance matched transmission circuit with analog-to-digital converter
An impedance matching transmission circuit for a transducer has a transmission medium connected to the transducer. A transmitting circuit is connected to the transmission medium with the transmitting circuit terminating in a reference circuit element. The transmitting circuit comprises an analog to digital converter having an analog input connected to the reference circuit element, and having a digital output. A digital to analog converter receives the digital output and generates an analog output signal in response thereto. A driver circuit is connected to the transmission medium and receives the analog output signal and supplies a driver signal to the transmission medium.
1. An ultrasound transmitter driver, comprising:
an analog-to-digital converter coupled to a reference resistor, wherein the analog-to-digital converter is configured to supply an encoded digital signal to a digital-to-analog circuit;
the digital-to-analog circuit configured to supply an analog signal to a programmable ultrasound-transmitter-driver circuit; and
the programmable ultrasound-transmitter-driver circuit configured to supply an ultrasound transmission to an ultrasound cable.
2. The driver of claim 1 , further comprising:
a plurality of resistors;
a plurality of comparators;
wherein one input of each comparator is coupled to the reference resistor and one input of each comparator is coupled to a different one of said plurality of resistors; and
wherein an output of each comparator is coupled to an encoding circuit.
3. The driver of claim 2 , wherein at least one of said plurality of resistors has a resistance smaller than the resistance of the reference resistor.
4. The driver of claim 2 , wherein at least one of said plurality of resistors has a resistance larger than the resistance of the reference resistor.
5. The driver of claim 1 , wherein the reference resistor has a resistance of 75 ohms.
6. The driver of claim 1 , wherein the digital-to-analog circuit comprises a plurality of AND gates.
7. A circuit comprising:
an analog-to-digital converter comprising a first logic circuit and a second logic circuit;
the first logic circuit comprising:
a first plurality of comparators, each comprising a first input lead, a second input lead, and an output lead, wherein each output lead is coupled to an encoding circuit;
a first reference resistor;
wherein each first input lead of each of said first plurality of comparators is coupled to the first reference resistor;
a first plurality of resistors;
wherein each second input lead of each of said first plurality of comparators is coupled to at least one of said first plurality of resistors;
the second logic circuit comprising:
a second plurality of comparators, each comprising a first input lead, a second input lead, and an output lead, wherein each output lead is coupled to an encoding circuit;
a second reference resistor;
wherein each first input lead of each of said second plurality of comparators is coupled to the second reference resistor;
a second plurality of resistors;
wherein each second input lead of each of said second plurality of comparators is coupled to at least one of said second plurality of resistors.
8. The circuit of claim 7 wherein each of the first plurality of resistors and each of the second plurality of resistors are paired with a transistor.
9. The circuit of claim 8 wherein the transistors are NMOS transistors.
10. The circuit of claim 9 wherein the NMOS transistors each have one gate, a source, and a drain, wherein the drains are coupled to a ground.
11. The circuit of claim 9 wherein the ratio of size between the resistors and transistors is linear.
12. The circuit of claim 8 wherein the transistors associated with the first plurality of resistors are each coupled to a voltage source.
13. The circuit of claim 8 wherein the transistors associated with the second plurality of resistors are each coupled to a ground.