IP Library › Granted Patent US 8,957,651
Granted Patent B2
US 8,957,651 · App. 13/159,090 · Granted Feb 17, 2015

User-configurable, efficiency-optimizing, power/energy conversion switch-mode power supply with a serial communications interface

Inventors: Terry Cleveland (Endicott, NY); Clifford Ellison, III (Campbell, NY); Scott Dearborn (Brackney, PA); Keith Pazul (Tempe, AZ)
Assignee: Microchip Technology Incorporated
H02M3/157
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Quick Facts
Patent No.
US 8,957,651
App. No.
13/159,090
Granted
Feb 17, 2015
Kind
B2
Abstract

An intelligent pulse width modulation (PWM) controller adapts a switch mode power supply (SMPS) system's operating parameters to optimize efficiency, remove hot spots and isolate faults by integrating a microcontroller, PWM digital circuits and analog circuits into a single integrated circuit, thereby reducing the number of external connections, silicon die area and integrated circuit packages. A communications interface is used to communicate with a host system for monitoring operating parameters of the SMPS, e.g., current, voltage, efficiency, operating temperature, diagnostics, etc. In addition, the communications interface may be used to alter the operating parameters (objectives) of the SMPS during operation thereof.

Claims (46)

1. A switch-mode power supply (SMPS), said SMPS comprising:

at least one power switch coupled to a voltage source;

a power inductor coupled to the at least one power switch;

a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage output of the SMPS; and

a mixed signal integrated circuit SMPS controller coupled to the voltage source, the at least one power switch, the power inductor and the regulated voltage output of the SMPS, wherein the SMPS controller comprises:

at least one driver connected to the at least one power switch;

a bias generator and current and voltage references providing bias voltages for said at least one driver;

a pulse width modulation (PWM) generator having an output coupled to and controlling the at least one driver;

a digital processor having a memory, the digital processor is coupled to and provides operating parameters to the PWM generator during operation thereof;

under/over voltage detector coupled with said digital processor;

an over current detector coupled with said digital processor;

a voltage comparison circuit for comparing the regulated output voltage to a reference voltage, wherein the voltage comparison circuit generates an error signal representative of a difference between the regulated output voltage and the reference voltage, and wherein the error signal is coupled to an error input of the PWM generator;

a power inductor current measurement circuit, wherein the power inductor current measurement circuit provides data to the digital processor that is representative of the current flowing through the power inductor, and

a communications interface coupled to the digital processor for providing user-configurable operating parameters to the SMPS;

wherein the digital processor optimizes operation of the SMPS by providing operating parameters to the SMPS controller for all operating conditions of the SMPS.

2. The SMPS according to claim 1 , wherein the communications interface further comprises providing monitoring and status of the SMPS to a user.

3. The SMPS according to claim 2 , wherein the communications interface is a serial communications interface.

4. The SMPS according to claim 1 , wherein the mixed signal integrated circuit SMPS controller is fabricated on an integrated circuit die.

5. The SMPS according to claim 1 , wherein the SMPS controller integrated circuit die is packaged in an integrated circuit package having external electrical connections.

6. The SMPS according to claim 1 , wherein the power inductor current measurement circuit comprises a series sense resistor in a main power path of the power inductor.

7. The SMPS according to claim 1 , wherein the power inductor current measurement circuit comprises a current sense transformer in a main current path of the SMPS.

8. The SMPS according to claim 1 , wherein the power inductor current measurement circuit comprises a circuit for measuring voltage drop across an upper MOSFET switch used as the at least one power switch.

9. The SMPS according to claim 1 , wherein the power inductor current measurement circuit comprises an auxiliary winding on the power inductor to provide an inductor voltage integral measurement.

10. The SMPS according to claim 1 , wherein the power inductor current measurement circuit comprises a matching complementary filter for measuring current through the power inductor.

11. A method for user-configurable optimization of a switch-mode power supply (SMPS) operation, said method comprising the steps of:

providing at least one power switch coupled to a voltage source;

providing a power inductor coupled to the at least one power switch;

providing a filter capacitor coupled to a load side of the power inductor that provides a regulated voltage from the SMPS; and

providing a mixed signal integrated circuit SMPS controller, wherein the SMPS controller facilitates:

coupling at least one driver to the at least one power switch,

providing bias voltages for said at least one driver;

controlling the at least one driver with a pulse width modulation (PWM) generator,

comparing the regulated voltage from the SMPS to a reference voltage with a voltage comparison circuit,

detecting an under/over voltage and an over current;

generating a voltage error signal representative of a difference between the regulated voltage and the reference voltage with the voltage comparison circuit,

coupling the voltage error signal to the PWM generator,

measuring current through the power inductor by a power inductor current measurement circuit;

providing a current output signal representative of the current flowing through the power inductor,

providing a digital processor having a memory, wherein the voltage error signal and the current output signal are coupled to inputs of the digital processor and the digital processor controls the PWM generator for adjusting operating parameters based upon the current output and voltage error signals and optimizing operation of the SMPS for all operating conditions thereof; and

providing a communications interface coupled to the digital processor for supplying user-configurable operating parameters to the SMPS.

12. The method according to claim 11 , further comprising the step of providing monitoring and status of the SMPS to a user with the communications interface.

13. The method according to claim 11 , wherein the step of measuring current through the power inductor comprises the step of measuring a voltage across a series sense resistor in a main power path of the power inductor, wherein the voltage is proportional to the current through the power inductor.

14. The method according to claim 11 , wherein the step of measuring current through the power inductor comprises the step of measuring current with a current sense transformer in a main current path of the SMPS.

15. The method according to claim 11 , wherein the step of measuring current through the power inductor comprises the step of measuring voltage drop across an upper MOSFET switch used as the at least one power switch.

16. The method according to claim 11 , wherein the step of measuring current through the power inductor comprises the step of measuring current with an auxiliary winding on the power inductor.

17. The method according to claim 11 , wherein the step of measuring current through the power inductor comprises the step of measuring current with a matching complementary filter.

Assignments (15)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2011
From: CLEVELAND, TERRY; ELLISON III, CLIFFORD; DEARBORN, SCOTT; PAZUL, KEITH
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 026469/0579 →
Continuity (2)
Provisional Application 61420090 · Dec 6, 2010
Related Publication 20120139518A1 · Jun 7, 2012