OP-AMP sharing technique to remove memory effect in pipelined circuit
This document describes a new op-amp sharing technique for pipeline ADC without memory effect. The key features of this technique are: the usage of negative impedance converter and scaled replica of the op-amp input device to achieve zero error voltage, which in turns achieve low power dissipation due to the removal of the tradeoff between op-amp sharing and memory effect. With this technique much lower operation of pipeline ADC can be achieved for applications of data communications and image signal processing.
1. An operational amplifier circuit, comprising:
a first operational amplifier comprising a first positive input coupled to ground, a first negative input coupled to an input signal, a first output, and a parasitic capacitor coupled to the first negative input;
a second operational amplifier comprising a second positive input coupled to the first positive input, a second negative input coupled to the first negative input, and a second output, wherein the second output is coupled to the second negative input;
a capacitor coupled between the second negative input and the second output;
wherein the first output comprises no memory effect when the operational amplifier circuit is shared by multiple stages of a pipelined circuit.
2. The operational amplifier circuit of claim 1 , wherein the second operational amplifier has a gain of A, the parasitic capacitor has a value of C PAR , and the capacitor has a value of C PAR /(A−1).
3. The operational amplifier circuit of claim 2 , wherein A=2.
4. The operational amplifier circuit of claim 1 , wherein the capacitor neutralizes the parasitic capacitor.
5. The operational amplifier circuit of claim 1 , wherein an input capacitance of the first operational amplifier is zero.
6. A pipelined circuit, comprising:
a first circuit coupled to an operational amplifier circuit during a first period; and
a second circuit coupled to the operational amplifier circuit during a second period;
the operational amplifier circuit, comprising:
a main amplifier comprising a parasitic capacitor;
a negative impedance converter coupled to the main amplifier; and
a capacitor coupled to the negative impedance converter to offset the parasitic capacitor.
7. The pipelined circuit of claim 6 , wherein the negative impedance converter has a gain of A, the parasitic capacitor has a value of C PAR , and the capacitor has a value of C PAR /(A−1).
8. The pipelined circuit of claim 7 , wherein A=2.
9. The pipelined circuit of claim 6 , wherein an input capacitance of the main amplifier is zero.
10. A pipelined circuit, comprising:
a first circuit coupled to an operational amplifier circuit during a first period;
a second circuit coupled to the operational amplifier during a second period;
the operational amplifier circuit comprising:
a first operational amplifier comprising a first positive input coupled to ground, a first negative input coupled to an input signal, a first output, and a parasitic capacitor coupled to the first negative input;
a second operational amplifier comprising a second positive input coupled to the first positive input, a second negative input coupled to the first negative input, and a second output, wherein the second output is coupled to the second negative input;
a capacitor coupled between the second negative input and the second output;
wherein the operational amplifier circuit generates no memory effect.
11. The pipelined circuit of claim 10 , wherein the second operational amplifier has a gain of A, the parasitic capacitor has a value of C PAR , and the capacitor has a value of C PAR /(A−1).
12. The pipelined circuit of claim 11 , wherein A=2.
13. The pipelined circuit of claim 10 , wherein an input capacitance of the first operational amplifier is zero.
14. The pipelined circuit of claim 10 , wherein the pipelined circuit is an analog-to-digital converter.
15. A method of operating a pipelined circuit, comprising:
coupling a first circuit coupled to an operational amplifier circuit during a first period; and
coupling a second circuit to the operational amplifier during a second period;
wherein the operational amplifier circuit comprises:
a first operational amplifier comprising a first positive input coupled to ground, a first negative input coupled to an input signal, a first output, and a parasitic capacitor coupled to the first negative input;
a second operational amplifier comprising a second positive input coupled to the first positive input, a second negative input coupled to the first negative input, and a second output, wherein the second output is coupled to the second negative input;
a capacitor coupled between the second negative input and the second output; and
wherein the operational amplifier circuit generates no memory effect during the second period.
16. The method of claim 15 , wherein the second operational amplifier has a gain of A, the parasitic capacitor has a value of C PAR , and the capacitor has a value of C PAR /(A−1).
17. The method of claim 16 , wherein A=2.
18. The method of claim 15 , wherein the pipelined circuit is an analog-to-digital converter.
19. The method of claim 15 , wherein an input capacitance of the first operational amplifier is zero.
20. The method of claim 15 , wherein the step of coupling a first circuit to an operational amplifier circuit during a first period utilizes one or more switched capacitors, and the step of coupling a second circuit to the operational amplifier during a second period utilizes one or more switched capacitors.