Mask free protection of work function material portions in wide replacement gate electrodes
In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.
1. A method of forming a semiconductor structure including a field effect transistor (FET), said method comprising:
forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity;
forming a gate dielectric over said top surface of said semiconductor substrate in said gate cavity;
forming a work function material layer on said gate dielectric;
forming a dielectric material portion on an horizontal portion of said work function material layer within said gate cavity;
etching said work function material layer, wherein a remaining portion of said work function material layer becomes a work function material portion; and
forming a conductive material portion over said dielectric material portion and said work function material portion, wherein a gate electrode of said field effect transistor comprises said conductive material portion and said work function material portion.
2. The method of claim 1 , wherein said forming of said dielectric material portion comprises:
depositing a dielectric material layer on said work function material layer; and
planarizing said dielectric material layer employing said work function material layer as a stopping layer.
3. The method of claim 2 , wherein said forming of said dielectric material portion further comprises recessing a remaining portion of said dielectric material layer employing physically exposed portions of said work function material layer as an etch mask.
4. The method of claim 3 , wherein a topmost surface of said dielectric material portion is recessed below a topmost surface of said planarization dielectric layer by said recessing of said remaining portion of said dielectric material layer.
5. The method of claim 3 , wherein said etching of said work function material layer comprises recessing said work function material layer below a topmost surface of said dielectric material portion employing said dielectric material portion as an etch mask.
6. The method of claim 1 , wherein said forming of said conductive material portion further comprises:
depositing a conductive material layer on said dielectric material portion and said work function material portion;
planarizing said conductive material layer; and
recessing a remaining portion of said conductive layer after said planarizing of said conductive material layer below a topmost surface of said planarization dielectric layer.
7. The method of claim 1 , further comprising forming a gate cap dielectric on said conductive material portion by filling a remaining portion of said gate cavity with a gate cap dielectric material and planarizing said gate cap dielectric material.
8. The method of claim 1 , further comprising:
forming a disposable gate structure on said semiconductor substrate prior to forming said planarization dielectric layer; and
planarizing said planarization dielectric layer, wherein a topmost surface of said disposable gate dielectric is coplanar with a top surface of said planarization dielectric layer after said planarizing, and said gate cavity is formed by removing said disposable gate structure.
9. The method of claim 1 , wherein said semiconductor structure includes another field effect transistor (FET), and said method further comprises forming another gate cavity laterally surrounded by said planarization dielectric layer on said semiconductor substrate, wherein another top surface of said semiconductor substrate is exposed at a bottom of said another gate cavity, wherein said work function material layer fills an entirety of said another gate cavity during formation of said work function material layer in said gate cavity.
10. The method of claim 9 , wherein said forming of said dielectric material portion comprises:
depositing a dielectric material layer on said work function material layer; and
planarizing said dielectric material layer employing said work function material layer as a stopping layer, wherein said dielectric material layer is not present over a portion of said work function material layer that fills said entirety of said another gate cavity after said planarizing of said dielectric material layer.
11. The method of claim 1 , wherein said forming the work function material layer comprises depositing a stack of a first titanium nitride layer, a tantalum carbide layer and a second titanium nitride layer.
12. The method of claim 1 , wherein said forming the work function material layer comprises depositing a metallic material selected from the group consisting of Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, TaN, Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof.
13. A method of forming a semiconductor structure including a field effect transistor (FET), said method comprising:
forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity;
forming a gate dielectric over said top surface of said semiconductor substrate in said gate cavity;
forming a work function material layer on said gate dielectric;
forming a dielectric material portion on an horizontal portion of said work function material layer within said gate cavity, said dielectric material portion has a topmost surface that is recessed below a topmost surface of said planarization dielectric layer;
etching said work function material layer, wherein a remaining portion of said work function material layer becomes a work function material portion; and
forming a conductive material portion over said dielectric material portion and said work function material portion, wherein a gate electrode of said field effect transistor comprises said conductive material portion and said work function material portion.
14. The method of claim 13 , wherein said forming the work function material layer comprises depositing a stack of a first titanium nitride layer, a tantalum carbide layer and a second titanium nitride layer.
15. The method of claim 13 , wherein said forming the work function material layer comprises depositing a metallic material selected from the group consisting of Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, TiAl, TaN, Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, a stack thereof, a conductive oxide thereof, a conductive nitride thereof, an alloy thereof, and a combination thereof.
16. The method of claim 13 , further comprising:
forming a disposable gate structure on said semiconductor substrate prior to forming said planarization dielectric layer; and
planarizing said planarization dielectric layer, wherein a topmost surface of said disposable gate dielectric is coplanar with a top surface of said planarization dielectric layer after said planarizing, and said gate cavity is formed by removing said disposable gate structure.
17. The method of claim 13 , wherein said semiconductor structure includes another field effect transistor (FET), and said method further comprises forming another gate cavity laterally surrounded by said planarization dielectric layer on said semiconductor substrate, wherein another top surface of said semiconductor substrate is exposed at a bottom of said another gate cavity, wherein said work function material layer fills an entirety of said another gate cavity during formation of said work function material layer in said gate cavity.