3D semiconductor device and structure
A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal transistors, the second structure overlaying the first single crystal transistors, where at least one of the second single crystal transistors is at least partially self-aligned to at least one of the first single crystal transistors; and at least one thermal conducting path from at least one of the first single crystal transistors and second single crystal transistors to an external surface of the device.
1. A 3D semiconductor device, comprising:
a first layer comprising first transistors each comprising a single crystal silicon channel;
a second layer comprising second transistors each comprising a single crystal silicon channel, said second layer overlaying said first transistors,
wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and
a third layer comprising third transistors each comprising a single crystal silicon channel, said third layer overlaying said second transistors,
wherein a plurality of said third transistors form a logic circuit, and
wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error; and
wherein said first layer thickness is less than one micron.
2. The 3D semiconductor device according to claim 1 ,
wherein said second layer thickness is less than one micron.
3. The 3D semiconductor device according to claim 1 ,
wherein said first layer comprises a floating body memory cell.
4. The 3D semiconductor device according to claim 1 , further comprising:
wherein said first layer comprises independently addressable double-gate transistors.
5. The 3D semiconductor device according to claim 1 ,
a memory array,
wherein said memory array comprises said first layer and said second layer, and
wherein said memory array comprises source lines comprising single crystal silicon.
6. The 3D semiconductor device according to claim 1 ,
wherein said 3D semiconductor device comprises an electrically modifiable resistive element.
7. The 3D semiconductor device according to claim 1 ,
wherein at least one of said first transistors are directly connected to at least one of said second transistors.
8. A 3D semiconductor device, comprising:
a first layer comprising first transistors each comprising a single crystal silicon channel;
a second layer comprising second transistors each comprising a single crystal silicon channel, said second layer overlaying said first transistors,
wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and
a third layer comprising third transistors each comprising a single crystal silicon channel, said third layer overlaying said second transistors,
wherein a plurality of said third transistors form a logic circuit, and
wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error.
9. The 3D semiconductor device according to claim 8 ,
wherein said second layer thickness is less than one micron.
10. The 3D semiconductor device according to claim 8 ,
wherein said first layer comprises a floating body memory cell.
11. The 3D semiconductor device according to claim 8 , further comprising:
wherein said first layer comprises independently addressable double-gate transistors.
12. The 3D semiconductor device according to claim 8 ,
wherein said first layer thickness is less than one micron.
13. The 3D semiconductor device according to claim 8 ,
wherein said 3D semiconductor device comprises an electrically modifiable resistive element.
14. The 3D semiconductor device according to claim 8 ,
wherein at least one of said first transistors are directly connected to at least one of said second transistors.
15. A 3D semiconductor device, comprising:
a first layer comprising first transistors each comprising a single crystal silicon channel;
a second layer comprising second transistors each comprising a single crystal silicon channel, said second layer overlaying said first transistors,
wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and
a third layer comprising third transistors each comprising a single crystal silicon channel, said third structure overlaying said second transistors,
wherein a plurality of said third transistors form a logic circuit, and
wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error; and
a memory control line, said memory control line is embedded in said second structure and comprises single crystal silicon.
16. The 3D semiconductor device according to claim 15 ,
wherein said second layer thickness is less than one micron.
17. The 3D semiconductor device according to claim 15 ,
wherein said first layer comprises a floating body memory cell.
18. The 3D semiconductor device according to claim 15 , further comprising:
wherein said first layer comprises independently addressable double-gate transistors.
19. The 3D semiconductor device according to claim 15 ,
wherein said 3D semiconductor device comprises an electrically modifiable resistive element.
20. The 3D semiconductor device according to claim 15 ,
wherein at least one of said first transistors are directly connected to at least one of said second transistors.